Abstract: An electronic watch comprising a level setting circuit which consists of a resistive device and a switching element connected between a switch and a power source. The resistance value of the switching element is much smaller than that of the resistive device and the switching element is rendered non-conductive when the switch is in its on state and is rendered conductive when the switch is in its off state.

Abstract: A clock pulse generating apparatus comprises a pulse generator for generating a pulse signal of a predetermined cycle, a frequency divider including a plurality of frequency division stages for frequency dividing an output pulse from the pulse generator, a circuit for subtracting at a predetermined ratio the number of clock pulses passing through a given frequency division stage in the frequency divider, a pulse control circuit including an external operation terminal for variably adding the number of pulses passing through another frequency division stage in the frequency divider, and a timing setting circuit for imparting a pulse subtracting timing and pulse adding timing to the pulse subtracting circuit and pulse control circuit, respectively.

Abstract: An electronic timepiece circuit wherein time data is shifted through a closed loop formed of a memory circuit, correction circuit and adder to count time upon receipt of a timing pulse, the memory circuit being composed of a plurality of static complementary MOS transistor type random access memory cells arranged in matrix form.

Abstract: An electronic music box circuit is provided which includes a pulse generator, a read only memory having address lines to be energized in a predetermined order by the output pulse signals from the pulse generator and memory cells arranged in accordance with a given melody, and a frequency-divider which divides the frequency of the output pulse signal from the pulse generator to produce a plurality of signals with different frequencies. In the read only memory, when one of the address lines is energized, a musical scale signal selection circuit and a signal level selection circuit are energized so that an output signal with a frequency selected from the output signals of the frequency divider is generated from the scale signal selection circuit while at the same time an output signal with a selected signal level is generated from the level selection circuit. The output signals from the scale signal and level signal selection circuits are supplied to a loudspeaker thereby to generate a predetermined sound.

Abstract: The setting circuit comprises first and second switches; a first signal generating circuit which generates a pulse signal each time the first switch is closed; a second signal generating circuit for generating 0 and 1 level output signals from a first output terminal when the second switch is opened and closed and a pulse signal from a second output terminal each time the second switch is opened; a ring counter circuit including cascade connected first to third shift registers each connected to receive the pulse signal from the second signal generating circuit at the reset terminal thereof, said ring counter operating as a 3 digit ring counter when the second switch is opened but as a four digit ring counter when the second switch is closed, thereby producing control signals for setting the display mode and the correction mode of the electronic timepiece from the first output terminal of the signal generating circuit and predetermined output terminals of the ring counter circuit.

Abstract: The time correction circuit comprises a switch, a first shift register circuit including two cascade connected shift registers driven by a 32 Hz clock pulse for shifting an electric signal generated by the operation of the switch, a second shift register circuit connected to the first shift register circuit and including two cascade connected shift registers driven by 1 Hz clock pulse for detecting the fact that whether the switch is maintained operated for an interval longer than a predetermined interval or not, a NOR gate circuit connected to receive the output from the two shift registers of the first shift register circuit, an AND gate circuit connected to receive the output signals from the first and second shift register circuits and a clock pulse having a predetermined frequency and an OR gate circuit connected to receive the output signals from the NOR gate circuit and the AND gate circuit.