Abstract: A semiconductor integrated circuit design apparatus (100) includes a delay analysis unit (102) which analyzes a static delay in respective paths of a semiconductor integrated circuit, a noise generation unit (104) which generates noise information based on a predetermined noise definition, a voltage fluctuation level analysis unit (106) which analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the noise information, and a timing verification unit (108) which makes the delay analysis unit (102) analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis, wherein the noise generation unit (104) generates noise information on noise applied at predetermined application timing, and the timing verification unit (108) verifies the timing for each noise applied with the predetermined application timing.