Abstract: The transmitting side encodes a digital signal to be transmitted by using a code not containing any DC component, and transmits the digital signal without using any carrier. The receiving side performs decoding corresponding to encoding for the received signal, and restores the original digital signal.

Abstract: A spread-spectrum demodulator includes a spreading code generating section, correlation value computing section, data signal demodulating section, peak signal detecting section, and spreading code generation control section. The spreading code generating section generates a spreading code for correlating with a received spread signal. The correlation value computing section computes a correlation value between the spread signal and the spreading code output from the spreading code generating section. The data signal demodulating section detects the peak of an output from the correlation value computing section and demodulates a data signal on the basis of the detected peak. The peak signal detecting section detects the peak of the output from the correlation value computing section. The spreading code generation control section changes the shifting direction of the spreading code relative to the spread signal every time a peak is detected by the peak signal detecting section.

Abstract: The transmitting side encodes a digital signal to be transmitted by using a code not containing any DC component, and transmits the digital signal without using any carrier. The receiving side performs decoding corresponding to encoding for the received signal, and restores the original digital signal.

Abstract: In the dual modulus prescaler circuit, an output terminal of the first multi-input logic gate circuit is connected to a data input terminal of a first D flip-flop circuit; output terminals of the first to (n-2)th D flip-flop circuits are, respectively, connected to data input terminals of the second to (n-1)th D flip-flop circuits; output terminals of the (n-1)th and nth D flip-flop circuits are connected to input terminals of the first multi-input logic gate circuit; the second multi-input logic gate circuit is connected to the output terminal of the (n-1)th D flip-flop circuit and receives a switching signal; and an output terminal of the second multi-input logic gate circuit is connected to a data input terminal of the nth D flip-flop circuit. Moreover, all the aforementioned connections are connections using differential signals.

Abstract: A mixer circuit used in a radio receiver for mixing two frequencies and providing an intermediate frequency which is the difference of the two frequencies. Excellent image rejection is provided by decreasing an amplitude error and a phase error of an output IF signal in differential form.

Abstract: A spread-spectrum demodulator includes a spreading code generating section, correlation value computing section, data signal demodulating section, peak signal detecting section, and spreading code generation control section. The spreading code generating section generates a spreading code for correlating with a received spread signal. The correlation value computing section computes a correlation value between the spread signal and the spreading code output from the spreading code generating section. The data signal demodulating section detects the peak of an output from the correlation value computing section and demodulates a data signal on the basis of the detected peak. The peak signal detecting section detects the peak of the output from the correlation value computing section. The spreading code generation control section changes the shifting direction of the spreading code relative to the spread signal every time a peak is detected by the peak signal detecting section.

Abstract: A phase-locked loop comprises a phase detector receiving an externally supplied reference signal and a feedback signal, a charge pump connected to an output of the phase detector, a loop filter configured to extract a low-frequency component from an output of the charge pump, and a voltage controlled oscillator having an input connected to the output of the loop filter and an output connected to the feedback signal supplied to the phase detector. The charge pump comprises a first switch that controls outputting a positive current based on the output of the phase detector, a second switch that controls outputting a negative current based on the output of the phase detector, a third switch connected between the first switch and the second switch to control an output to the loop filter, and a switching control signal input terminal that receives a switching control signal for controlling a switching operation of the third switch.

Abstract: A phase-locked loop comprises a phase detector receiving an externally supplied reference signal and a feedback signal, a charge pump connected to an output of the phase detector, a loop filter configured to extract a low-frequency component from an output of the charge pump, and a voltage controlled oscillator having an input connected to the output of the loop filter and an output connected to the feedback signal supplied to the phase detector. The charge pump comprises a first switch that controls outputting a positive current based on the output of the phase detector, a second switch that controls outputting a negative current based on the output of the phase detector, a third switch connected between the first switch and the second switch to control an output to the loop filter, and a switching control signal input terminal that receives a switching control signal for controlling a switching operation of the third switch.

Abstract: An input stage for adjusting the gain or conductance Gm depending upon a control voltage applied and an output stage for securing a sufficiently high output impedance and a sufficiently wide output dynamic range are connected between the voltage source and the ground in parallel with each other.

Abstract: In an image-rejection receiver having a first frequency conversion stage (1, 2, 9) having a pair of frequency mixers (1,2) each supplied external radio frequency signal (RF) and first local frequency signal (LOCAL1) with quadrature phase relations (9), a second frequency conversion stage (3-6, 10) having two pairs of frequency mixers (3-4, 5-6) at each output of each first stage mixer and second local frequency signal (LOCAL2) with quadrature phase relations (10), and an adder (7) and a subtractor (8) for providing sum and difference of amplitude of outputs of said second frequency conversion stage to provide inphase component (BBI) and quadrature-phase component (BBQ), no filter is used for removing an undesirable image signal which is generated in frequency conversion. A control circuit (11) is provided to keep accurate quadrature phase relations for said first local frequency signal, and said second local frequency signal, by measuring D.C. component of a product of outputs of two of mixers.

Abstract: A transconductance amplifier has an input stage and an output stage. The input stage includes a differential input circuit for converting a differential voltage signal applied thereto into a differential current signal, a first pair of regulated cascode circuits for adjusting output voltages of the differential input circuit depending upon a control voltage applied thereto, and an input section of a pair of current mirror circuits for mirroring the differential current signal from the differential input circuit. The differential input circuit, the first pair of regulated cascode circuits, and the input section of the pair of current mirror circuits are connected in series with each other between a voltage source and a ground.

Abstract: A quadrature signal generation system which has a pair of input terminals for receiving a first A.C. signal and a second A.C. signal. The first A.C. signal and the second A.C. signal have a predetermined frequency and a phase relation of approximate 90° with each other. The system also has a multiplier circuit for providing a product of the first A.C. signal and the second A.C. signal, resulting in a third A.C. signal. Furthermore, the system has a square-difference circuit for providing a difference of a square of the first A.C. signal and a square of the second A.C. signal, the difference being a fourth A.C. signal. The frequency of the third A.C. signal, and the fourth A.C. signal are equal to twice the frequency of the first A.C. signal and the second A.C. signal, and the third A.C. signal and the fourth A.C. signal have a fine phase relation of 90° with each other.

Abstract: A mixer circuit used in a radio receiver for mixing two frequencies (RF, LO) and providing an intermediate frequency (IF) which is difference of two frequencies (RF-LO) with excellent performance of rejection of an image frequency (RF+LO) has a differential amplifier (2e) for amplifying an input RF signal (RF) to provide amplified output in differential form, and a plurality of differential pairs (2a, 2b, 2c, 2d) for mixing an output of said differential amplifier (2e) and a local signal (LO-I, LO-Q) to provide an output IF signal (IF-I, IF-Q). Each output of the amplified RF signal is commonly applied to inphase branch (I) and quadrature branch (Q) of the differential pairs. Sources of each differential pairs (2a, 2b, 2c, 2d) and sources of said differential amplifier (2e) are coupled with a ground through an impedance circuit (3a, 3b, 3c) which has high impedance for operation frequency (RF, LO) and is short-circuited for D.C. current.

Abstract: A mixer circuit for frequency conversion operates with low power supply voltage lower than 1 V. The circuit comprises a first pair of N-channel MOS transistors and a second pair of N-channel MOS transistors each receiving differential local frequency signal, and a third pair of P-channel MOS transistors receiving differential radio frequency signal. Each pair of transistors is coupled in series with a parallel resonance circuit which operates as a constant current source. A drain of each transistor of the third pair of transistors is connected to a junction of a first pair and a second pair of transistors and a parallel resonance circuit. An output intermediate frequency signal, which differs between the local frequency and the radio frequency, is obtained at the junction of drains of the first and the second pair of transistors and load resistors.

Abstract: A fractional-N frequency divider system generates an output signal having frequency of an input signal divided by a desired frequency division ratio (N+A/M) in which N is an integer and A/M is a fraction, A.ltoreq.M, and includes a programmable frequency divider receiving input frequency and providing divided frequency in which division ratio (N, N+1) is an integer and is externally supplied, a selector supplying one of the externally supplied integers (N, N+1) to the divider according to a selection signal, and a fractional part set having a first counter initialized to count M, a second counter initialized to count A, and a logic circuit for supplying the selection signal according to the counters. The counters are decremented by an output of the divider and reach zero when they receive M and A number of pulses, respectively. The second counter stops counting operation when it reaches zero.