Abstract: To provide an interrupt control device for avoiding an unwanted transition to a low power mode without a decrease in software quality. The interrupt control device receives an interrupt, and also receives a switching instruction to switch a target device from a normal power mode to the low power mode, the switching instruction being included in a transition program showing a transition procedure from the normal to low power mode. The interrupt control device manages an interrupt state, by switching between a disable state of disabling any interrupt, a first enable state of enabling an interrupt in a period of the transition procedure, and a second enable state of enabling an interrupt in a period other than the period of the transition procedure. If the interrupt is received in the first enable state, the interrupt control device abandons the switching instruction when subsequently receiving the switching instruction.

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.