Abstract: A frequency counter detects a sampling frequency of an input digital signal. If a control circuit is notified that the sampling frequency of the input digital signal changes according to a signal from the frequency counter, it temporarily stops accumulation of input digital signal in a data memory. An operation processing circuit continues operation processing on the input digital signal accumulated in the data memory at that time. After the operation processing terminates, the control circuit reads a program and processing data corresponding to the changed sampling frequency from a program memory and a coefficient/offset data memory and sets them in the operation processing circuit. After that, the operation processing circuit restarts operation processing.

Abstract: A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.