Patents by Inventor Tsung-Che TSAI
Tsung-Che TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150137174Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.Type: ApplicationFiled: January 9, 2015Publication date: May 21, 2015Inventors: Jam-Wem Lee, Tzu-Heng Chang, Tsung-Che Tsai, Ming-Hsiang Song
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Publication number: 20150097264Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che TSAI, Jam-Wem LEE
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Patent number: 8963200Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.Type: GrantFiled: June 20, 2012Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jam-Wem Lee, Tzu-Heng Chang, Tsung-Che Tsai, Ming-Hsiang Song
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Publication number: 20150029622Abstract: A semiconductor device is disclosed that includes a first well of a first conductivity type, a second well of a second conductivity type, a plurality of first regions, a second region and a plurality of electrodes. The first regions are of the first conductivity type and are formed in the second well. The second region is of the second conductivity type and is formed in the first well. Each of the electrodes is formed upon the second well and between adjacent two first regions of the first regions.Type: ApplicationFiled: July 26, 2013Publication date: January 29, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ti SU, Wun-Jie LIN, Tsung-Che TSAI, Jen-Chou TSENG
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Patent number: 8906767Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.Type: GrantFiled: December 13, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Hung Cho Wang
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Publication number: 20140264604Abstract: An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height.Type: ApplicationFiled: November 26, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Che Tsai, Yi-Feng Chang, Jam-Wem Lee
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Patent number: 8809961Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.Type: GrantFiled: October 17, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
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Publication number: 20140145249Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Che Tsai, Yi-Feng Chang, Jam-Wem Lee
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Publication number: 20140131765Abstract: A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Che Tsai, Yi-Feng Chang, Jam-Wem Lee
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Publication number: 20140094009Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.Type: ApplicationFiled: December 13, 2013Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Hung Cho Wang
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Publication number: 20140035039Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.Type: ApplicationFiled: October 17, 2013Publication date: February 6, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che TSAI, Jam-Wem LEE, Yi-Feng CHANG
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Publication number: 20140028466Abstract: A method for monitoring energy source by a server receives a service request transmitted by a user terminal, requesting to gather statistics of an energy usage situation of a monitor object corresponding to an energy sensor. The server obtains energy input quantity and energy output quantity of the monitor object detected by the energy sensor according to the service request. The server gathers the statistics of the energy usage situation of the monitor object according to the energy input quantity and the energy output quantity.Type: ApplicationFiled: March 23, 2013Publication date: January 30, 2014Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: TSUNG-CHE TSAI
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Publication number: 20130341676Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jam-Wem Lee, Tzu-Heng Chang, Tsung-Che Tsai, Ming-Hsiang Song
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Patent number: 8610220Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.Type: GrantFiled: May 16, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Roger Wang
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Publication number: 20130307080Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Roger Wang
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Patent number: 8587071Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.Type: GrantFiled: April 23, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
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Publication number: 20130277745Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.Type: ApplicationFiled: April 23, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Che TSAI, Jam-Wem LEE, Yi-Feng CHANG