Patents by Inventor Tsung-chi Hsu

Tsung-chi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190243079
    Abstract: The present invention is a flip-chip photodetector, comprising a carrier and a back-illuminated chip having a central portion and a peripheral portion, wherein the central portion has a greater thickness than the peripheral portion; the peripheral portion is provided with a plurality of metal pillars connected to the carrier, and the back illuminated chip is connected to the carrier by the plurality of metal pillars; further, the plurality of the metal pillars are provided on the back-illuminated chip by electroless plating.
    Type: Application
    Filed: June 19, 2018
    Publication date: August 8, 2019
    Inventors: Kuo-Hao LEE, Tsung-Chi HSU, Ming-Chih LAI
  • Patent number: 10283652
    Abstract: The present invention provides an electrode stack structure capable of preventing moisture from entering a photodiode, comprising: a semiconductor layer; an inner electrode layer provided on the semiconductor layer; a dielectric layer coating a sidewall of the semiconductor layer; an intermediate metal layer provided on, bonded to, and in electrical conduction with the inner electrode layer, wherein the intermediate metal layer has a bottom side extending over and covering a portion of the dielectric layer to provide airtightness; and an anti-reflection layer coating on an outer side of the semiconductor layer, an outer side of the intermediate metal layer, and an outer side of the dielectric layer, with a groove formed in the anti-reflection layer by leaving a predetermined area of a top side of the intermediate metal layer uncoated or by removing a portion of the anti-reflection layer that coats the predetermined area of the top side of the intermediate metal layer, and an outer electrode layer plated on th
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 7, 2019
    Assignee: LUXNET CORPORATION
    Inventors: Kuo-Hao Lee, Tsung-Chi Hsu, Ming-Chih Lai
  • Publication number: 20120008896
    Abstract: The present invention relates to an integrate optics for multiplexer transceiver module, comprising: a substrate, a multiplexer, a first waveguide coupling device, a second waveguide coupling device and a third waveguide coupling device. In the present invention, the semiconductor materials and the semiconductor process are used to integrate variety of optical devices on a single semiconductor substrate (chip) by way of modular design and miniaturization, so as to carry out an integrated optics communication framework with high efficiency and low cost. Moreover, in the present invention, a plurality of optical receivers are integrated on the substrate by means of flip-chip bonding, so that, not only the objective of integrating the optical devices is accomplished but also the intensity of laser optical signal is increased.
    Type: Application
    Filed: June 10, 2011
    Publication date: January 12, 2012
    Applicant: NATIONAL TSING-HUA UNIVERSITY
    Inventors: Ming-Chang Lee, Kai-Ning Ku, Chung-Yung Wang, Kuo-Chung Huang, Tsung-Chi Hsu, Chung-Hsin Fu, Lin-Yu Tai
  • Patent number: 6670692
    Abstract: A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: December 30, 2003
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ching-chang Shih, Chun-an Tu, Tsung-chi Hsu, Wei-feng Lin, Ming-huan Lu