Patents by Inventor Tsung-Chieh Ho

Tsung-Chieh Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20200126988
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 23, 2020
    Inventors: Yu-Lin YANG, Chia-Cheng HO, Chih Chieh YEH, Cheng-Yi PENG, Tsung-Lin LEE
  • Patent number: 10483262
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lin Yang, Chia-Cheng Ho, Chih Chieh Yeh, Cheng-Yi Peng, Tsung-Lin Lee
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 7727878
    Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 1, 2010
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Cheng-Hsueh Su, Hsing-Fu Lu, Tsung-Chieh Ho, Shyh-Ing Wu
  • Patent number: 7518241
    Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
  • Publication number: 20080044774
    Abstract: The present invention relates to a method for exposing twice by two masks in a semiconductor process, which includes: (a) providing a substrate having a surface; (b) forming a negative-type photosensitive material on the surface of the substrate; (c) providing a first mask having a first pattern; (d) performing a first exposure procedure on the negative-type photosensitive material by utilizing a first light beam through the first mask; (e) providing a second mask having a second pattern, wherein the entire texture of the second pattern is substantially identical to that of the first pattern; and (f) performing a second exposure procedure on the negative-type photosensitive material by utilizing a second light beam through the second mask. Thus, the negative-type photosensitive material will not be damaged and will not cause yield loss.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 21, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Hsueh SU, Tsung-Chieh HO
  • Publication number: 20070232052
    Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.
    Type: Application
    Filed: December 28, 2006
    Publication date: October 4, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Cheng-Hsueh Su, Hsing-Fu Lu, Tsung-Chieh Ho, Shyh-Ing Wu
  • Publication number: 20070045848
    Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 1, 2007
    Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu