Patents by Inventor Tsung-Chieh Hsiao
Tsung-Chieh Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250044270Abstract: A system for notifying environmental pollution status includes wireless environment sensing devices and a portable wireless environmental pollution status notification device. The wireless environment sensing devices, respectively arranged in the different sensing locations of a physical environment, respectively store the sensing locations and respectively sense pollution related information corresponding to the different sensing locations to output the pollution related information and the sensing locations corresponding thereto. The portable wireless environmental pollution status notification device, wirelessly connected to the plurality of wireless environment sensing devices and located in the physical environment, receives the pollution related information and the sensing locations corresponding thereto and generates notification signals based on the pollution related information and the sensing locations corresponding thereto.Type: ApplicationFiled: July 15, 2024Publication date: February 6, 2025Inventors: CHIA-JUI YANG, HERMAN CHUNGHWA RAO, CHUN-CHIEH KUO, HUA-PEI CHIANG, SHUI-SHU HSIAO, ZHENG-XIANG CHANG, CHYI-DAR JANG, TSUNG-JEN WANG, CHE-YU LIAO, CHIH-MIN CHAN, TENG-CHIEH YANG, CHANG-HUNG HSU
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Publication number: 20250046667Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.Type: ApplicationFiled: October 6, 2023Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Chih-Pin Chiu, Hsin-Feng Chen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250046678Abstract: A method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. The first trenches extend partially into the carrier substrate for a distance less than the second trenches. The method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. The first conductive features remain partially embedded in the carrier substrate.Type: ApplicationFiled: January 8, 2024Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
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Publication number: 20250046756Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.Type: ApplicationFiled: January 4, 2024Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
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Patent number: 12218186Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.Type: GrantFiled: February 7, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chiung Tu, Hsiang-Ku Shen, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
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Publication number: 20250035603Abstract: A positioning pollutant-measuring system includes a cloud server, a wireless base station, an automatic moving vehicle, and a positioning pollutant-measuring device. The automatic moving vehicle carries the positioning pollutant-measuring device and passes through different locations. The positioning pollutant-measuring device receives location related parameters from the wireless base station and measures the air flow rates or the air humidity of the different locations to adjust a resolution for measuring pollutants corresponding to the different locations.Type: ApplicationFiled: June 24, 2024Publication date: January 30, 2025Inventors: Chia-Jui YANG, HERMAN CHUNGHWA RAO, Chun-Chieh KUO, Hua-Pei CHIANG, Shui-Shu HSIAO, Zheng-Xiang CHANG, Chyi-Dar JANG, Tsung-Jen WANG, Che-Yu LIAO, Chih-Min CHAN, Teng-Chieh YANG, CHANG-HUNG HSU
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Publication number: 20250038074Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.Type: ApplicationFiled: December 1, 2023Publication date: January 30, 2025Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240421063Abstract: One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.Type: ApplicationFiled: June 16, 2023Publication date: December 19, 2024Inventors: Tsung-Chieh Hsiao, Chung-Yun Wan, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240397829Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Chieh HSIAO, Yu-Feng YIN, Liang-Wei WANG, Dian-Hau CHEN
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Publication number: 20240387617Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer over a first insulating layer and forming a first dielectric layer over the first conductive layer. A second conductive layer is formed over a first portion of the first dielectric layer. A second dielectric layer is formed over the second conductive layer. A third conductive layer is formed over the second dielectric layer and the second portion of the first dielectric layer. A third dielectric layer is formed over the third conductive layer. A first conductive contact is formed contacting the first conductive layer. A second conductive contact is formed contacting the third conductive layer. The second conductive layer is an electrically floating layer.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Wen-Chiung TU, Chen-Chiu HUANG, Dian-Hau CHEN
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Publication number: 20240379531Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
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Publication number: 20240379361Abstract: A semiconductor device structure and a formation method are provided. The method includes forming an opening in a semiconductor body, and the semiconductor body is p-type doped. The method also includes introducing n-type dopants into the semiconductor body to form a modified portion near the opening, and the modified portion is p-type doped. The method further includes forming a dielectric layer along the sidewalls and the bottom of the opening. In addition, the method includes forming a conductive structure over the dielectric layer to fill the opening.Type: ApplicationFiled: May 11, 2023Publication date: November 14, 2024Inventors: Chih-Chuan SU, Liang-Wei WANG, Tsung-Chieh HSIAO, Dian-Hau CHEN
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Publication number: 20240379734Abstract: A semiconductor device includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes. The MIM capacitor is disposed in an interlayer dielectric (ILD) layer disposed over a substrate. The one or more first electrodes are connected to a side wall of a first via electrode disposed in the ILD layer, and the one or more second electrodes are connected to a side wall of a second via electrode disposed in the ILD layer. In one or more of the foregoing or following embodiments, the one or more insulating layers include a high-k dielectric material.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Publication number: 20240371920Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.Type: ApplicationFiled: July 20, 2024Publication date: November 7, 2024Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Patent number: 12133469Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.Type: GrantFiled: September 28, 2021Date of Patent: October 29, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh Hsiao, Yu-Feng Yin, Liang-Wei Wang, Dian-Hau Chen
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Patent number: 12080753Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.Type: GrantFiled: June 19, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
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Publication number: 20240282837Abstract: A first conductive pad disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A through-substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner disposed between the TSV and the substrate in a second direction different from the first direction.Type: ApplicationFiled: June 15, 2023Publication date: August 22, 2024Inventors: Kuan-Hsun Wang, Tsung-Chieh Hsiao, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240274653Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.Type: ApplicationFiled: April 15, 2024Publication date: August 15, 2024Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Tsung-Chieh Hsiao, Ying-Yao Lai, Dian-Hau Chen
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Publication number: 20240266334Abstract: An integrated semiconductor device is provided. The integrated semiconductor device includes a first semiconductor structure having a first IC, and a second semiconductor structure stacked above the first semiconductor structure and having a second IC. The second semiconductor structure has a first surface facing the first semiconductor structure and a second surface facing away from the first semiconductor structure. The integrated semiconductor device also includes a thermal dissipation structure having a first portion partially through the first IC and a second portion fully through the second semiconductor structure and exposed at the second surface of the second semiconductor structure. The second portion may be outside of the second IC.Type: ApplicationFiled: February 7, 2023Publication date: August 8, 2024Inventors: Ke-Gang Wen, Liang-Wei Wang, Dian-Hau Chen, Tsung-Chieh Hsiao
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Publication number: 20240258177Abstract: Embodiments of the present disclosure relate to methods for warpage correction. Particularly, embodiments of the present disclosure relate to substrate level warpage correction by depositing one or more warpage correction layers in a redistribution layer (RDL) structure, a front side warpage correction layer, and/or a back side warpage correction layer. In some embodiments, the warpage correction layer is a high stress dielectric layer. Characteristics of the warpage correction layer, such as stress level, and thickness, may be determined according to the substrate level warpage and the die level packaging scheme using an auto process control program.Type: ApplicationFiled: January 31, 2023Publication date: August 1, 2024Inventors: Tsung-Chieh HSIAO, Chih Hsin YANG, Dian-Hau CHEN