Abstract: An electronic device includes two speakers, a single functional chip, a parameter extraction circuit, an audio processing module, a gain adjusting circuit and a current detecting unit. The current detecting unit is disposed in the functional chip for detecting the driving current of the two speakers. The functional chip provides the driving voltage of the two speakers based on an output signal and converts the analogue current/voltages of the two speakers into digital current/voltages. The parameter extraction circuit acquires the parameter of each speaker based on the digital current/voltages. The audio processing module acquires the gains of various physical quantities based on the parameter of each speaker and determines the final gain of each physical quantity. The gain adjusting circuit provides the output signal by adjusting the gain of an input signal based on the final gain of each physical quantity.

Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.

Abstract: The present invention relates to a device of internal probe pads used in failure analysis. The invention provides a circuitry which comprises a plurality of probe pads placed in the last metal layer of a die. Each probe pad is divided into several conductive regions, and each conductive region is selectively connected to one of the contacts of the internal circuitry within the die by interconnects. The circuitry within the die is placed into a mode by supplying signals to parts of the plurality of probe pads, wherein at least one probe pad is used to transmit the signals into the circuitry and another one of the probe pads is grounded.

Abstract: A laser fuse comprising of a conventional laser fuse and an NMOS transistor. The two voltage source terminals of the fuse are connected to a low voltage and a high voltage respectively. A laser window is formed on the high voltage source terminal serving as a fuse-breaking port for a laser beam. The gate terminal of the NMOS transistor is connected to a position between the two input terminals of the fuse. One source/drain terminal of the NMOS transistor is connected to an input terminal while the other source/drain terminal of the NMOS transistor is connected to an output terminal. When the fuse is completely broken, the NMOS transistor is non-conductive because a voltage lower than the threshold voltage of the NMOS transistor is supplied to the gate terminal. Even if the fuse is only partially broken, resistance at the second voltage source is increased so much that the voltage at the gate terminal of the NMOS transistor is again lower than the threshold voltage.

Abstract: A method for fabricating self-aligned DRAM cell with stack capacitor, which is comprised of providing a semiconductor substrate having a plurality of oxide isolation regions and MOS transistors formed thereon, each of the MOS transistors with a cap layer of silicon nitride and a silicon nitride spacer, wherein two adjacent MOS transistors are formed between two oxide isolation regions and the two adjacent MOS transistors share a source/drain region therebetween. Forming a plurality of first oxides on each of the oxide isolation regions and each of the MOS transistors by photolithography and etching method. Thereafter, utilizing photolithography and etching method, forming a plurality of conductive regions of MOS-like structure each of which with a cap layer of silicon nitride and a silicon nitride spacer, across over two first oxides on the two adjacent MOS transistors.

Abstract: A package with an electrical static discharge resistor. A chip is attached on a carrier with bumps and contacts. The carrier couples with the chip through the bumps. Electrical static discharge resistors between the bumps and the contacts are on the carrier.

Abstract: A method for fabricating a metal oxide semiconductor having a double-diffused drain, which is applicable to the fabrication of an electrostatic discharge protection present fabrication method for a metal oxide semiconductor does not require additional masks. Only an additional ion implantation step is sufficient to form a double diffused drain metal-oxide-semiconductor for an electrostatic discharge protection circuit, in which the electrostatic discharge protective capability of the electrostatic discharge protection circuit is enhanced.

Abstract: A method and a testing system for measuring contact resistance of a pin on an integrated circuit. An RC circuit is coupled to the integrated circuit, and a response signal of a testing signal input to the integrated circuit is monitored. The response signal has a time dependent voltage V′. Another time dependent voltage V1 for the testing signal through the RC circuit and a voltage drop across an internal circuit of the integrated circuit is illustrated. Comparing V′ with V1, whether the contact resistance of the pin being tested is allowable can be determined according to the ratings or specification of the integrated circuit.

Abstract: A method for forming a stacked capacitor. A gate is formed on a provided substrate. Doped regions are formed in the substrate beside the gate. A first dielectric layer is formed over the substrate. A part of the first dielectric layer is removed to form a node contact opening and a bit line contact opening. The bit line contact opening is located between the gate and separates the gate into two portions. Spacers are formed on sidewalls of the node contact openings and on the bit line contact opening. Conductive material is formed to fill the openings to form a bit line and a landing pad. A second dielectric layer having a opening exposing the landing pad is formed on the first dielectric layer. Conductive material is formed to fill the opening to form a lower electrode. A dielectric film and a upper are formed on the lower electrode.

Abstract: A method for fabricating a DRAM with a silicide layer formed on a gate of a MOS transistor in a memory region is provided. The method not only forms a first silicide layer on a first MOS transistor at the periphery region as a conventional structure but also forms a second silicide layer on a gate of a second MOS transistor, at the memory region. The second silicide layer is formed on a polysilicon layer before the polysilicon is patterned to form a gate so that the gate includes the second silicide layer on it top. An insulating layer is also formed over the substrate before the polysilicon is patterned so that the insulating layer serve as a mask when an interchangeable source/drain region of the second MOS transistor is formed.

Abstract: A method of manufacturing an electrostatic discharge protective circuit for DRAM is disclosed. In the market, two gates are first formed on a substrate. A silicon oxide layer is formed over the substrate. Next, a contact window is formed in the silicon oxide layer to expose a common source/drain region between the two gates in the substrate and parts of the two gates. Since the two gates are formed at the same time, there is no problem with alignment accuracy in the formation of the contact window therebetween. Then, the contact window is filled by a conductive material, such as doped polysilicon, which is used to electrically connect the two gates and the common source/drain region.

Abstract: A dynamic random access memory's (DRAM's) electrostatic discharge (ESD) protection circuit structure and its method of manufacture, wherein the ESD protection circuit and the capacitors are formed at the same time. The ESD protection circuit has a heavily doped drain structure so that hot carriers can be recruited for discharging electrostatics and a better electrostatic discharge protection can be achieved. Furthermore, no additional electrostatic discharge implant operations are necessary.