Abstract: An image building module includes an image builder, a signal-shielding flexible film, and a signal shielding cover. The image builder includes a first image capturing element and a processing chip. The first image capturing element is used for capturing a first image. The processing chip is used for processing the first image. The signal-shielding flexible film covers the processing chip. The signal shielding cover covers the image builder and the signal-shielding flexible film. The signal shielding cover has a first through hole exposing the first image capturing element.

Abstract: An image building module includes an image builder, a signal-shielding flexible film, and a signal shielding cover. The image builder includes a first image capturing element and a processing chip. The first image capturing element is used for capturing a first image. The processing chip is used for processing the first image. The signal-shielding flexible film covers the processing chip. The signal shielding cover covers the image builder and the signal-shielding flexible film. The signal shielding cover has a first through hole exposing the first image capturing element.

Abstract: A trench MOSFET structure formed in a semiconductor substrate and method of forming the same are disclosed. The trench MOSFET includes a capacitor having a capacitor dielectric layer formed of an oxide-un-doped poly-oxide in the trench bottom. Firstly, the trenches are formed in a p-well of the epi-layer of an n-type impurity doped substrate through a lithographic and an etch step. Next, a gate oxide layer and an intrinsic polysilicon layer are successively formed, and a HTO layer is deposited on the trench bottom to form the oxide-un-doped poly-oxide dielectric layer. Subsequently a doped polysilicon layer is filled into the trench as a trench gate. Then, processes of source contact regions and gate contacts are followed. Finally a drain contact is formed on a rear surface of the substrate.

Abstract: A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer is removed. In addition, a sidewall structure is formed at laterals of the gate protruded from the surface of the trench structure. Hence the source structure and the first conductive layer formed at the surface of the gate can be isolated through the sidewall structure. When the trench power semiconductor device is processed at high frequency, the net resistance of the gate can be reduced by the first conductive layer, and thus the electrical properties thereof can be elevated.