Abstract: A through-silicon via self-routing circuit includes a plurality of through-silicon vias (TSVs) and a plurality of planar die. The plurality of planar die are connected by the plurality of TSVs. And each one of the plurality of planar die includes a built-in self-tester, a built-in self-routing switching network, and a core circuit. The built-in self-tester has a plurality of valid-bit leads and a plurality of through-silicon via leads to connect the plurality of TSVs. The built-in self-routing switching network is connected to the built-in self-tester, for selecting from the plurality of TSVs for conducting. The core circuit has a to plurality of I/O leads linked to the built-in self-routing switching network.

Abstract: A memory address remapping architecture is applied to execute an address remapping method for repairing a main memory. A valid flag and an essential flag in a TCAM corresponding to at least one subcube address in a spare memory are initialized, and the main memory is checked to find out some faulty cell addresses. The Hamming distance between the subcube address and the faulty cell address is calculated, and the faulty cell address is merged into the subcube address by a masked bits concentrator when the Hamming distance is not larger than an address-width degree of the subcube address and the merged number of the subcube address is not larger than a threshold value.

Abstract: A memory address remapping architecture is applied to execute an address remapping method for repairing a main memory. A valid flag and an essential flag in a TCAM corresponding to at least one subcube address in a spare memory are initialized, and the main memory is checked to find out some faulty cell addresses. The Hamming distance between the subcube address and the faulty cell address is calculated, and the faulty cell address is merged into the subcube address by a masked bits concentrator when the Hamming distance is not larger than an address-width degree of the subcube address and the merged number of the subcube address is not larger than a threshold value.

Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.

Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.

Abstract: A Berger invert code encoding and decoding method is disclosed. The method includes steps: Selecting logic value 0 or 1 to represent the stable and unstable states respectively. Calculating the stable bit count and the unstable-bit count of the codeword. Checking whether the unstable bit count is larger than the stable bit count or not. Setting the Invert Bit to the unstable state for indicating the inversion when the unstable bit count is larger than the stable bit count. Resetting the Invert Bit to the stable state for indicating the non-inversion when the unstable bit count is not larger than the stable bit count. Concatenating the Invert Bit to the codeword as a new codeword.