Abstract: A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Abstract: A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Abstract: The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.

Abstract: A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

Abstract: A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

Abstract: A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.