Patents by Inventor Tsung-Han CHUANG

Tsung-Han CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170556
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.
    Type: Application
    Filed: February 20, 2023
    Publication date: May 23, 2024
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20240087877
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Te CHIU, Kechuang LIN, Houng-Chi WEI, Chia-Chu KUO, Bing-Han CHUANG
  • Publication number: 20230420520
    Abstract: In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
    Type: Application
    Filed: January 5, 2023
    Publication date: December 28, 2023
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20230420513
    Abstract: An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230411527
    Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20230395655
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes at least two active strip regions, a hybrid fin structure, and a gate stack. The hybrid fin structure is disposed between the at least two active strip regions. The gate stack is across the at least two active strip regions and the hybrid fin structure. A portion of the hybrid fin structure exposed by the gate stack is free of a high dielectric constant material.
    Type: Application
    Filed: June 5, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20230369456
    Abstract: A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.
    Type: Application
    Filed: March 10, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Chih-Hao Wang, Chien Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang
  • Publication number: 20230197856
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric layer formed over the first bottom layer. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric layer.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 22, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230178600
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.
    Type: Application
    Filed: May 16, 2022
    Publication date: June 8, 2023
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20230144099
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20230113269
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.
    Type: Application
    Filed: March 3, 2022
    Publication date: April 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230065208
    Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Tsung-Han CHUANG, Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230028900
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Application
    Filed: March 11, 2022
    Publication date: January 26, 2023
    Inventors: Zhi-Chang LIN, Chien Ning YAO, Shih-Cheng CHEN, Jung-Hung CHANG, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20220416036
    Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: December 29, 2022
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11458533
    Abstract: A measuring device includes a furnace, a draining vessel, a loader and a computing system for physical properties. The draining vessel with molten metal fluid is in the furnace. The loader accumulates the molten metal fluid from the draining vessel. The computing system includes a recording unit, transform unit, computing unit and processor. The recording unit records the vessel information. By the assumed physical parameters and the vessel information, the transform unit transforms a weight of the molten metal fluid in the loader into a first length criterion, and the computing unit simulates the flowing of the molten metal fluid to have a second length criterion. The processor minimizes the difference of the first and the second length criterion by changing the assumed physical parameters. The physical properties of the molten metal fluid are determined when the difference is minimized.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 4, 2022
    Assignee: National Central University
    Inventors: Chih-Ang Chung, Ya-Huan Lee, Tsung-Han Chuang, Tsung-Hsuan Chiang, Chih-Shan Yen, Jeng-Rong Ho, Jason Shian-Ching Jang
  • Publication number: 20210060637
    Abstract: A measuring device includes a furnace, a draining vessel, a loader and a computing system for physical properties. The draining vessel with molten metal fluid is in the furnace. The loader accumulates the molten metal fluid from the draining vessel. The computing system includes a recording unit, transform unit, computing unit and processor. The recording unit records the vessel information. By the assumed physical parameters and the vessel information, the transform unit transforms a weight of the molten metal fluid in the loader into a first length criterion, and the computing unit simulates the flowing of the molten metal fluid to have a second length criterion. The processor minimizes the difference of the first and the second length criterion by changing the assumed physical parameters. The physical properties of the molten metal fluid are determined when the difference is minimized.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Inventors: Chih-Ang CHUNG, Ya-Huan LEE, Tsung-Han CHUANG, Tsung-Hsuan CHIANG, Chih-Shan YEN, Jeng-Rong HO, Jason Shian-Ching JANG