Patents by Inventor Tsung-Han Ko

Tsung-Han Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363722
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting CHEN, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng
  • Patent number: 12094952
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting Chen, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
  • Publication number: 20240077802
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 7, 2024
    Inventors: Yu-Chung SU, Tsung-Han KO, Ching-Yu CHANG
  • Publication number: 20230242115
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor For Manufactuing Co., Ltd.
    Inventors: Ting-Ting CHEN, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
  • Patent number: 11626482
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ting Chen, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
  • Publication number: 20220285492
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ting CHEN, Chen-Han WANG, Keng-Chu LIN, Shuen-Shin LIANG, Tsu-Hsiu PERNG, Tsai-Jung HO, Tsung-Han KO, Tetsuji UENO, Yahru CHENG
  • Publication number: 20210200092
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.
    Type: Application
    Filed: November 13, 2020
    Publication date: July 1, 2021
    Inventors: Yu-Chung SU, Tsung-Han KO, Ching-Yu CHANG
  • Patent number: 10796910
    Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20200135452
    Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han KO, Joy CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 10573519
    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20190080901
    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.
    Type: Application
    Filed: February 27, 2018
    Publication date: March 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han KO, Joy CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 10157739
    Abstract: Disclosed is a method of forming a semiconductor device using a self-assembly (DSA) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (DSA) process over the first and the second orientation layers.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Ko, Ching-Yu Chang, Kuan-Hsin Lo
  • Publication number: 20180144928
    Abstract: Disclosed is a method of forming a semiconductor device using a self-assembly (DSA) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (DSA) process over the first and the second orientation layers.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Tsung-Han Ko, Ching-Yu Chang, Kuan-Hsin Lo
  • Patent number: 9892914
    Abstract: Disclosed is a method of forming a semiconductor device using a self-assembly (DSA) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (DSA) process over the first and the second orientation layers.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tsung-Han Ko, Ching-Yu Chang, Kuan-Hsin Lo
  • Publication number: 20170110319
    Abstract: Disclosed is a method of forming a semiconductor device using a self-assembly (DSA) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (DSA) process over the first and the second orientation layers.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Tsung-Han Ko, Ching-Yu Chang, Kuan-Hsin Lo