Patents by Inventor Tsung-Hsi Yang
Tsung-Hsi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240115681Abstract: Provided is a pharmaceutical composition including an active pharmaceutical ingredient, a toll-like receptor (TLR) agonist, a stimulator of interferon genes (STING) agonist, and a pharmaceutically acceptable carrier. Also provided are a method for inducing immune response and a method for treating or preventing cancer or an infectious disease, including administering an effective amount of the pharmaceutical composition to a subject in need thereof.Type: ApplicationFiled: September 28, 2023Publication date: April 11, 2024Applicant: National Health Research InstitutesInventors: Tsung-Hsien Chuang, Jing-Xing Yang, Jen-Chih Tseng, Zaida Nur Imana, Ming-Hsi Huang, Guann-Yi Yu
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Patent number: 11948971Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.Type: GrantFiled: August 10, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
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Publication number: 20230336498Abstract: A data bandwidth management method is provided. The data bandwidth management method is applied to a data bandwidth management device. The bandwidth management method includes the steps of obtaining one or more data bandwidth sharing configurations corresponding to one or more sharing devices; receiving a service request of a client device connected to the data bandwidth management device; and allocating data bandwidth of the one or more sharing devices to the client device based on the one or more data bandwidth sharing configurations in response to the service request of the client device.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventors: Tsung-Hsi YANG, Tzu-Wen CHANG
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Patent number: 11652105Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: GrantFiled: January 7, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Patent number: 11581425Abstract: A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.Type: GrantFiled: March 11, 2021Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsi Yang, Che-Yu Lin, Yi-Fang Pai, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
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Patent number: 11569084Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.Type: GrantFiled: March 11, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Che-Yu Lin, Chih-Chiang Chang, Chien-Hung Chen, Ming-Hua Yu, Tsung-Hsi Yang, Ting-Yi Huang, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20220384437Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Publication number: 20220293415Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Che-Yu LIN, Chih-Chiang CHANG, Chien-Hung CHEN, Ming-Hua YU, Tsung-Hsi YANG, Ting-Yi HUANG, Chii-Horng LI, Yee-Chia YEO
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Publication number: 20220293773Abstract: A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsi YANG, Che-Yu LIN, Yi-Fang PAI, Pei-Ren JENG, Chii-Horng LI, Yee-Chia YEO
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Publication number: 20220181440Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.Type: ApplicationFiled: February 21, 2022Publication date: June 9, 2022Inventors: Tsung-Hsi Yang, Ming-Hua Yu, Jeng-Wei Yu
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Patent number: 11315837Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.Type: GrantFiled: September 4, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, Tsung-Hsi Yang, Ming-Hua Yu
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Patent number: 11257908Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.Type: GrantFiled: August 16, 2019Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsi Yang, Ming-Hua Yu, Jeng-Wei Yu
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Publication number: 20220028856Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: ApplicationFiled: January 7, 2021Publication date: January 27, 2022Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Publication number: 20210376073Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.Type: ApplicationFiled: August 10, 2021Publication date: December 2, 2021Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
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Patent number: 11101347Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.Type: GrantFiled: July 1, 2019Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
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Patent number: 10879128Abstract: A semiconductor device includes a first semiconductor fin extending from a substrate, a first dielectric fin extending from the substrate adjacent a first side of the first semiconductor fin and a second dielectric fin extending from the substrate adjacent a second side of the first semiconductor fin, a first gate stack over and along sidewalls of the first semiconductor fin, the first dielectric fin, and the second dielectric fin, a first epitaxial source/drain region in the first semiconductor fin and extending from the first dielectric fin to the second dielectric fin, and an air gap between the first epitaxial source/drain region and the substrate, the air gap extending between the first dielectric fin and the second dielectric fin.Type: GrantFiled: August 2, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu, Chii-Horng Li
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Publication number: 20200402862Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Yi-Jing Lee, Tsung-Hsi Yang, Ming-Hua Yu
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Patent number: 10770359Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.Type: GrantFiled: April 22, 2019Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, Tsung-Hsi Yang, Ming-Hua Yu
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Publication number: 20200176560Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.Type: ApplicationFiled: July 1, 2019Publication date: June 4, 2020Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
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Publication number: 20200135861Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.Type: ApplicationFiled: August 16, 2019Publication date: April 30, 2020Inventors: Tsung-Hsi Yang, Ming-Hua Yu, Jeng-Wei Yu