Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: A method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes planarizing a first portion of the dielectric layer and planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized. In addition, the method includes forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: Disclosed herein is a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.

Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.