Patents by Inventor Tsung-Hsing LU

Tsung-Hsing LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200020603
    Abstract: Generally, the present disclosure provides example embodiments relating to a package attached to a printed circuit board (PCB). In an embodiment, a structure includes a PCB. The PCB has ball pads arranged in a matrix. Outer ball pads are along one or more outer edges of the matrix, and each of the outer ball pads has a first solder-attach area. Inner ball pads are interior to the matrix, and each of the inner ball pads has a second solder-attach area. The first solder-attach area is larger than the second solder-attach area.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventors: Pei-Haw TSAO, Tsung-Hsing LU, Li-Huan CHU
  • Patent number: 10510633
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10506712
    Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10373901
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; a polymeric layer disposed between the second surface of the first substrate and the third surface of the second substrate; a first conductive via extended through the first substrate, the second substrate and the polymeric layer; a second conductive via extended through the first substrate, the second substrate and the polymeric layer; and a third conductive via extended through the first substrate, the second substrate and the polymeric layer, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, the first conductive via and the third conductive via are configured to connect to electrical ground.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10304793
    Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao
  • Publication number: 20180151498
    Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing LU, Pei-Haw TSAO