Abstract: A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.

Abstract: A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.

Abstract: The present disclosure provides a method for ripening a resistive random access memory (RRAM). The method includes: obtaining a first RRAM, wherein the first RRAM includes a plurality of memory cells; performing a forming operation and an initial reset operation on the first RRAM to form a plurality of specific memory cells in the memory cells; reading a specific number of the specific cells, and determining a ripening cycle parameter according to the specific number; and performing a ripening operation on the first RRAM based on the ripening cycle parameter to ripen the first RRAM as a second RRAM.

Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.

Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.

Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

Abstract: The disclosure provides a method for obtaining optimal operating condition of a resistive random access memory (RRAM). The method includes: retrieving an RRAM chip and performing a forming operation and an initial reset operation thereto based on a first operating condition; segmenting the RRAM chip into blocks; performing a set operation to each of the blocks based on various operating voltages; obtaining a fail bit value of each of the blocks; generating an operating characteristic curve related to the RRAM chip based on the fail bit value of each of the blocks and the operating voltages, wherein the operating characteristic curve has a lowest fail bit value and an operating voltage window; and when the lowest fail bit value and the operating voltage window satisfy a first condition and a second condition, respectively, determining the first operating condition is an optimal operating condition of the RRAM chip.

Abstract: A lens array is disposed on a substrate and includes a plurality of converging lenses. The converging lenses are configured to project light beams and are arranged along a first direction. Two of the light beams respectively converged by adjacent two of the converging lenses at least partially overlap with each other by geometry of the adjacent two converging lenses, a distance between the adjacent two converging lenses, or a combination thereof.

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

Abstract: A lighting system including a LED light source, a convex lens, and a light guide post disposed between the LED light source and the convex lens. The light guide post includes a light emitting portion and a light collecting portion connected to the light emitting portion. The light emitting portion has a light guide post-light emitting surface facing the convex lens. The light collecting portion has an internal reflective surface including at least an elliptical surface having a first focal point and a second focal point. The second focal point is located between the first focal point and the convex lens, and the second focal point is located inside the light guide post.

Abstract: A lens array is disposed on a substrate and includes a plurality of converging lenses. The converging lenses are configured to project light beams and are arranged along a first direction. Two of the light beams respectively converged by adjacent two of the converging lenses at least partially overlap with each other by geometry of the adjacent two converging lenses, a distance between the adjacent two converging lenses, or a combination thereof.

Abstract: A lighting system including a LED light source, a convex lens, and a light guide post disposed between the LED light source and the convex lens. The light guide post includes a light emitting portion and a light collecting portion connected to the light emitting portion. The light emitting portion has a light guide post-light emitting surface facing the convex lens. The light collecting portion has an internal reflective surface including at least an elliptical surface having a first focal point and a second focal point. The second focal point is located between the first focal point and the convex lens, and the second focal point is located inside the light guide post.

Abstract: A method for forming a memory device is provided. The method includes forming a plurality of memory cells. The method also includes performing a first baking on the memory cells. The method further includes setting a specified current, and after performing the first baking, performing a test process on the memory cells. The test process includes reading the current of the memory cells. When the read current of the memory cells is larger than or equal to the specified current, the test process of the memory cell is done. When the read current of the memory cells is smaller than the specified current, a re-forming process is performed on the memory cells to form a plurality of re-formed memory cells, and then the test process is performed on the re-formed memory cells.

Abstract: A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.

Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.