Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.

Abstract: A display device includes a first display unit emitting a green light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak and an intensity of the first peak.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A portable communication apparatus equipped with basic communication functions and game functions include a first body and a second body. The first body has a bi-directional axle, a display screen and a first keyboard area on the top surface. The second body is hinged on the bi-directional axle, and includes a second keyboard area on the top surface thereof and a third keyboard area on the back surface. The second body is turnable around the bi-directional axle relative to the first body to generate movements around two axes, to turn the second keyboard area or the third keyboard area, to face the display screen and to fold over the first body. When the second body is turned relative to the first body, the image displayed on the display screen also is turned to a selected angle.

Abstract: A portable device is capable of automatically determining if the portable device is moving and achieving a specific function with a button-free procedure. The portable device includes an embedded microprocessor and an acceleration detector. The acceleration detector can determine if the portable device is moving by detecting a vibration of the portable device and thus prohibit the portable device from entering the locked mode. In addition, when the portable device is moving or inclining with specific sequential operations by the effect of an external force, the acceleration detector can generate a sensing signal and the microprocessor can obtain a specific command in response to the comparison between the sensing data and a sample database, so that the microprocessor can achieve the specific function.

Abstract: The present invention provides a new IC packaging and its manufacturing methods. This technology simultaneously combines Flip Chip (FC), Ball Grid Array (BGA), and Chip on Chip (COC) packages to form a vertically stacked IC such that multiple semiconductor chips can be integrated into a single, small factor IC product. Each semiconductor chip as well as the substrate of the final IC product can be manufactured, tested, and assembled separately under its own optimal manufacturing conditions, thereby increasing yield, lowering manufacturing cost, and shortening processing time. Another advantage of this new technology is that the length of the interconnects between the semiconductor chips as well as between each semiconductor chip and the substrate is shorter than those of known IC packages. The reduction of the length of the rerouting lines enhances electrical performance because inductance of the signal path is greatly reduced.