Patents by Inventor Tsung Jing Wu

Tsung Jing Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022958
    Abstract: A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-You TAI, Ling-Sung Wang, Chen-Chieh Chiang, Jung-Chi Jeng, Po-Yuan Su, Tsung Jing Wu
  • Publication number: 20230411537
    Abstract: Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 21, 2023
    Inventors: Cheng-You Tai, Sung-Hsin Yang, Tsung Jing Wu, Jung-Chi Jeng, Ling-Sung Wang, Ru-Shang Hsiao
  • Publication number: 20230299213
    Abstract: Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Cheng-You Tai, Ling-Sung Wang, Ru-Shang Hsiao, Jung-Chi Jeng, Sung-Hsin Yang, Tsung Jing Wu