Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.

Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.

Abstract: A cell self-assembly array chip comprises a first substrate, a second substrate and a plurality of spacer elements. The first substrate, the spacer elements and the second substrate are stacked to be one in turn, wherein the spacer elements are annularly arranged at interval and disposed on the second substrate, so as to define a cell self-assembly region and at least one drawing channel. Furthermore, because the liquid portion of cell suspension horizontally and radially passed the drawing channel outward and the radially outward pulling force generated by the evaporation effect of the liquid portion, so as to cause the cells are arranged by the cell self-assembly array to the cell self-assembly region. The present invention further provides a manufacturing method of a cell self-assembly array chip to solve the conventional problems which is difficult to culture living cells and not easy to apply optical observation.