Patents by Inventor Tsung-Ju CHEN

Tsung-Ju CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266397
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11990509
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Publication number: 20240145250
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 2, 2024
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11908695
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20230274938
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 31, 2023
    Inventors: Hao-Ming TANG, Shu-Han CHEN, Yun-San CHIEN, Da-Yuan LEE, Chi On CHUI, Tsung-Ju CHEN, Yi-Hsin TING, Han-Shen WANG
  • Publication number: 20230126442
    Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.
    Type: Application
    Filed: May 9, 2022
    Publication date: April 27, 2023
    Inventors: Tsung-Ju Chen, Shu-Han Chen, Chun-Heng Chen, Chi On Chui
  • Publication number: 20220352313
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11430865
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11393900
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Publication number: 20210343533
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20210233997
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Application
    Filed: May 22, 2020
    Publication date: July 29, 2021
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11069531
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20200135474
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Application
    Filed: July 2, 2019
    Publication date: April 30, 2020
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Patent number: 9939353
    Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 10, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Fan-Gang Tseng, Jui-Chia Chang, Tsung-Ju Chen
  • Publication number: 20160061710
    Abstract: An apparatus for cell observation and a method for cell collection using the same are disclosed. The apparatus for cell selection comprises a first substrate having an opening; and a second substrate having a photoresist unit disposed on a surface thereof, wherein the photoresist unit comprises at least one notch and defines a space which is interconnected with the notch and corresponds to the opening of the first substrate.
    Type: Application
    Filed: March 25, 2015
    Publication date: March 3, 2016
    Inventors: Fan-Gang TSENG, Jui-Chia CHANG, Tsung-Ju CHEN
  • Publication number: 20140045254
    Abstract: A cell self-assembly array chip comprises a first substrate, a second substrate and a plurality of spacer elements. The first substrate, the spacer elements and the second substrate are stacked to be one in turn, wherein the spacer elements are annularly arranged at interval and disposed on the second substrate, so as to define a cell self-assembly region and at least one drawing channel. Furthermore, because the liquid portion of cell suspension horizontally and radially passed the drawing channel outward and the radially outward pulling force generated by the evaporation effect of the liquid portion, so as to cause the cells are arranged by the cell self-assembly array to the cell self-assembly region. The present invention further provides a manufacturing method of a cell self-assembly array chip to solve the conventional problems which is difficult to culture living cells and not easy to apply optical observation.
    Type: Application
    Filed: December 21, 2012
    Publication date: February 13, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Fan-Gang TSENG, Tsung-Ju CHEN, Yu-Cheng CHANG