Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.

Abstract: A device includes a first power transistor, a second power transistor electrically connected in series with the first power transistor, a first electrostatic discharge (ESD) detection circuit, and a first control circuit electrically connected to the first ESD detection circuit and the first power transistor.

Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: Systems and methods are provided for command execution. A stream-array data structure including a plurality of stream entries is received. One or more head pointers of one or more command chains are obtained from the stream entries. One or more source commands corresponding to the one or more head pointers are obtained in the command chains. A target command is selected from the one or more source commands based at least in part on a priority of the target command. The target command is executed, and removed from the command chains. The stream-array data structure is updated.

Abstract: An Electrostatic Discharge (ESD) clamp includes first power rail, a second power rail separate from the first power rail, and an ESD discharging circuit including a plurality of cascaded MOS transistors coupled between the second power rail and an electrical ground. A bias circuit is configured to turn on the ESD discharging circuit in response to an ESD event on the second power rail, and to turn off the ESD discharging circuit during a normal operation of the ESD clamp.

Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: A device includes a first power transistor, a second power transistor electrically connected in series with the first power transistor, a first electrostatic discharge (ESD) detection circuit, and a first control circuit electrically connected to the first ESD detection circuit and the first power transistor.

Abstract: An Electrostatic Discharge (ESD) clamp includes first power rail, a second power rail separate from the first power rail, and an ESD discharging circuit including a plurality of cascaded MOS transistors coupled between the second power rail and an electrical ground. A bias circuit is configured to turn on the ESD discharging circuit in response to an ESD event on the second power rail, and to turn off the ESD discharging circuit during a normal operation of the ESD clamp.

Abstract: A spindle motor includes a stator structure and a rotor structure coupled to the stator structure. The stator structure has a stator base, a magnetic conductive structure surrounding the stator base, and a first buffer structure provided in the gap defined by the stator base and the magnetic conductive structure and in contact with both the stator base and the magnetic conductive structure. Furthermore, a second buffer structure and a third buffer structure are respectively provided between the stator base and the casing and between the stator base and the base plate.

Abstract: A spindle motor includes a stator structure and a rotor structure coupled to the stator structure. The stator structure has a stator base, a magnetic conductive structure surrounding the stator base, and a first buffer structure provided in the gap defined by the stator base and the magnetic conductive structure and in contact with both the stator base and the magnetic conductive structure. Furthermore, a second buffer structure and a third buffer structure are respectively provided between the stator base and the casing and between the stator base and the base plate.

Abstract: Computer equipment using a plurality of BIOS versions. The equipment includes a selecting device, a memory device, and a CPU. The selecting device provides a selecting signal responding to the BIOS version. The memory device is coupled to the selecting device to store the BIOS version, and outputs the responding BIOS version according to the selecting signal. The CPU is coupled to the memory device to load the responding BIOS version.

Abstract: A spindle motor includes a stator structure and a rotor structure enclosing the stator structure. The stator structure has a stator base, a magnetic conductive structure surrounding the stator base, and a buffer structure provided in the gap defined by the stator base and the magnetic conductive structure and in contact with both the stator base and the magnetic conductive structure.

Abstract: An insulating layer is formed over a surface of a semiconductor substrate. A conductive film is formed over the insulating layer and separated from the semiconductor substrate. A shielding pattern is embedded within the semiconductor substrate and includes a plurality of isolation portions and a plurality of highly doped portions. The isolation portions are distributed within the semiconductor substrate for dividing the surface of the semiconductor into a plurality of regions unconnected with each other. The highly doped portions are formed within the semiconductor substrate and close to the surface, electrically insulated from each other by the isolation portions. The shielding pattern may further include a plurality of silicide layers formed on the highly doped portions and an ion implanted well for accommodating the isolation portions and the highly doped portions.

Abstract: Computer equipment using a plurality of BIOS versions. The equipment includes a selecting device, a memory device, and a CPU. The selecting device provides a selecting signal responding to the BIOS version. The memory device is coupled to the selecting device to store the BIOS version, and outputs the responding BIOS version according to the selecting signal. The CPU is coupled to the memory device to load the responding BIOS version.

Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: The present invention is a method for making intermetal dielectrics (IMD) on integrated circuits using a low dielectric constant (low k) spin-on polymers without via hole poisoning. A patterned conductive layer is used to form metal interconnection for the integrated circuits. A IMD layer is then formed by depositing sequentially three IMD layers, IMD1, IMD2 and IMD3 respectively. The IMD1 is deposited first and is a low k polymer. IMD2 composed of silicon nitride (Si.sub.3 N.sub.4) and a thick IMD3 composed of silicon oxide (SiO.sub.2) is deposited next. The IMD3 is planarized, and a photoresist mask is used to pattern openings in IMD3 to form a hard mask for etching the remaining via holes in IMD2 and IMD3. The IMD2 layer protects the low k polymer (IMD1) from damage while plasma ashing in oxygen is used to removal the photoresist mask.