Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Abstract: Apparatus and methods for reducing noise and distortion in current digital-to-analog converters (IDACs). Compensating capacitors may be connected to current sources in an IDAC. The compensating capacitors may be driven with signals 5 derived from the output of the IDAC to cancel transient current spikes that would otherwise occur on the output of the IDAC.

Abstract: Apparatus and methods for reducing noise and distortion in current digital-to-analog converters (IDACs) are described. Compensating capacitors may be connected to current sources in an IDAC. The compensating capacitors may be driven with signals derived from the output of the IDAC to cancel transient current spikes that would otherwise occur on the output of the IDAC.

Abstract: An analog-to-digital conversion that converts an input signal to an output signal by using multiple analog-to-digital converting circuits. A first analog-to-digital converting circuit generates a first signal based on the input signal and further outputs a feature signal of a first quantization error of the first analog-to-digital converting circuit. A second analog-to-digital converting circuit generates a second signal based on the input signal and the feature signal. The output combiner combines the first signal and the second signal to generate the output signal and thereby to reduce a quantization error factor in the output signal that is due to the first quantization error.

Abstract: A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal has a first signal segment followed by a second signal segment, and a voltage level of the first signal segment is unknown; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit; wherein a voltage of the supply power is settle before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.

Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Abstract: A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal comprises a first signal segment followed by a second signal segment; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit and selectively generating an output signal according to the output control signal; wherein the supply power is turned on before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.

Abstract: A signal processing apparatus for generating an output analog signal according to a raw digital signal is disclosed. The signal processing apparatus includes a DAC, a storage device, and an adjusting device. The storage device is utilized for storing a target mapping table equivalent to a combination of a predetermined correction mapping table and a DAC calibration mapping table corresponding to the DAC. The adjusting device is coupled to the DAC and the storage device, and is utilized for adjusting the raw digital signal to generate a calibrated digital signal according to the target mapping table stored in the storage device. The DAC converts the calibrated digital signal to generate the output analog signal.