Patents by Inventor Tsung-kai Yang

Tsung-kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404328
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 2, 2022
    Assignee: Nexchip Semiconductor Co., LTD
    Inventors: Chunlong Xu, Ching-Ming Lee, Tsung-kai Yang
  • Publication number: 20210384083
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 9, 2021
    Applicant: Nexchip Semiconductor Co., LTD
    Inventors: Chunlong Xu, Ching-Ming Lee, Tsung-kai Yang