Patents by Inventor Tsung-Lin Wu

Tsung-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250244879
    Abstract: A data storing method, a memory storage device, and a memory controller are provided. The method includes: obtaining a plurality of program/erase counts and a plurality of program/erase period values of a plurality of physical erasing units in a storage area; calculating a plurality of data cold and hot degrees according to the plurality of program/erase counts and the plurality of program/erase period values; selecting a first physical erasing unit according to the plurality of data cold and hot degrees, and selecting a second physical erasing unit according to the plurality of data cold and hot degrees; and writing data stored in the first physical erasing unit to the second physical erasing unit.
    Type: Application
    Filed: August 20, 2024
    Publication date: July 31, 2025
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Jian Hu, Tsung-Lin Wu, Qi-Ao Zhu, Chong Peng
  • Publication number: 20250244880
    Abstract: The invention provides a wear leveling method, a memory storage device, and a memory control circuit unit. The method includes: recording wear count values respectively corresponding to a plurality of physical units; obtaining a total of a plurality of first physical units, wherein a first wear count value corresponding to each of the first physical units meets a first condition; triggering a wear leveling operation in response to the total meeting a second condition; and in the wear leveling operation, moving valid data in at least one second physical unit to at least one of the plurality of first physical units. As a result, the wear leveling operation performed on the rewritable non-volatile memory module may be optimized.
    Type: Application
    Filed: August 20, 2024
    Publication date: July 31, 2025
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Xu Hui Cheng, Tsung-Lin Wu, Qi-Ao Zhu, Chong Peng
  • Publication number: 20250244901
    Abstract: A storage controller, a data reading method and a storage device. data reading method: identifying a plurality of logical addresses corresponding to files based on file read commands; determining a plurality of mapping tables corresponding to files based on logical addresses; loading a first mapping table corresponding to a first file to a first memory section of a buffer memory; identifying one or more second logical addresses of one or more second files corresponding to first mapping table among files or than first file; determining target content of first mapping table based on one or more second logical addresses, and copying target content to a second memory section of buffer memory; and from target content, finding a fourth physical address corresponding to a fourth logical address of a fourth file among second files, to read fourth data of fourth file, so as to respond to a fourth file read command.
    Type: Application
    Filed: August 19, 2024
    Publication date: July 31, 2025
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Zhenyu Xu, Kuai Cao, Yuting Niu, Tsung-Lin Wu, Qi-Ao Zhu
  • Publication number: 20250245101
    Abstract: A memory control method and a memory storage device, and the method includes: dividing each of the storage groups into a first or second storage group; receiving a first write command from a host system, in which the first write command includes first data and a first address; performing a first encoding process on the first data to obtain first parity data; storing the first data and the first parity data in a first physical programming cell indicated by the first address; determining whether a current storage group to which the first physical programming cell belongs is the first or second storage group; and in response to the current storage group being the first storage group, performing a second encoding process on the first physical programming cell to obtain second parity data of the first physical programming cell, and storing the second parity data of the first physical programming cell.
    Type: Application
    Filed: August 21, 2024
    Publication date: July 31, 2025
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Yuecong Liang, Yan Zheng, Kai-Di Zhu, Zhi Wang, Tsung-Lin Wu, Qi-Ao Zhu
  • Publication number: 20250239310
    Abstract: A voltage adjustment method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a first physical unit among the physical units based on a first read voltage to obtain a first count value, wherein the first count value reflects a total number of memory cells each having a threshold voltage lower than the first read voltage; obtaining a second count value based on a difference between the first count value and a first default value; bringing the second count value into a target formula to obtain a voltage adjustment parameter; adjusting the first read voltage to a second read voltage according to the voltage adjustment parameter; and reading the first physical unit based on the second read voltage.
    Type: Application
    Filed: August 22, 2024
    Publication date: July 24, 2025
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Jian Hu, Wan-Jun Hong, Tsung-Lin Wu, Qi-Ao Zhu, Chong Peng
  • Patent number: 12367139
    Abstract: Disclosed are a memory control method and a storage device. The storage device includes a memory controller and a memory module. The storage device is electrically connected to a host system. The memory control method includes: sending, by the host system, an identification instruction to the memory controller to obtain identification information of the memory module transmitted by the memory controller; generating a command sequence list corresponding to the memory module according to the identification information; transmitting the command sequence list to the memory controller; sending a corresponding invoke instruction to the memory controller according to execution requirements, for invoking and executing one of multiple command sequences in the command sequence list once or multiple times to control the memory module.
    Type: Grant
    Filed: March 16, 2025
    Date of Patent: July 22, 2025
    Assignee: Hosin Global Electronics Co., LTD
    Inventors: Xiao Min Chen, Tsung-Lin Wu, Chao-Yu Chen, Qi Ming Zhu, Wu Du, Kai Qiang Meng, Hai Liang Wu, Jie Zhang, Wei Wang
  • Publication number: 20250231712
    Abstract: A command information distribution method includes: arranging a plurality of first command queues used to cache in parallel command information from a flash translation layer; arranging a plurality of second command queues used to cache in parallel command information to be transmitted to the rewritable non-volatile memory module; extracting first command information from a first target queue among the first command queues according to weight information corresponding to the first command queues; performing information format processing on the first command information to generate second command information; and distributing the second command information to a second target queue among the second command queues. A memory storage device is also provided.
    Type: Application
    Filed: October 28, 2024
    Publication date: July 17, 2025
    Applicant: Hosin Global Electronics Co., LTD
    Inventors: Wei ZHONG, Kaidi ZHU, Zhi WANG, Tsung-Lin Wu, Qiao ZHU
  • Publication number: 20250231874
    Abstract: The disclosure discloses a storage controller, a memory management method, and a storage device, the memory management method including: identifying a current power mode of a host system; obtaining a target command from a command queue; in response to determining that the target command is used to enable a write booster mode, determining whether the power mode is a highest level; in response to determining that the power mode is the highest level, determining whether a cache block currently in use is a physical block of a triple-level cell type; in response to determining that the cache block currently in use belongs to the triple-level cell type, freezing the cache block of the triple-level cell type; using a physical block of a single-level cell type as a new cache block to write cache data; and enabling the write booster mode, and sending an enabling completed response.
    Type: Application
    Filed: September 2, 2024
    Publication date: July 17, 2025
    Applicant: Hefei Kaimeng Technology Co., Ltd.
    Inventors: Lihong GUO, Jun YIN, Kaidi ZHU, Zhi WANG, Tsung-Lin Wu, Qiao Zhu
  • Publication number: 20250083432
    Abstract: A method of making a mouse pad contains: bonding and hot-press molding a body and a cloth by using a first mold and a second mold. The body is made of polyurethane (PU), the second mold includes a cavity, and a size of the cavity of the second mold is equal to a predetermined size of the body, and a guide rib surrounds the cavity. The method comprising steps of: 1) flattening the body; 2) bonding the cloth on the body; 3) cutting the body in a predetermined; 4) hot-press molding the body and the cloth; 5) sublimation printing; and 6) hot-press molding to trim the mouse pad by using the first mold and of the guide rib the second mold.
    Type: Application
    Filed: July 14, 2024
    Publication date: March 13, 2025
    Inventor: Tsung-Lin Wu
  • Patent number: 12009379
    Abstract: An image sensor is provided. The image sensor includes a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, and the first photoelectric conversion component includes: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 11, 2024
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Chin-Chuan Hsieh
  • Patent number: 11557598
    Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tsung-Lin Wu
  • Publication number: 20220130848
    Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Tsung-Lin Wu
  • Patent number: 11257837
    Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tsung-Lin Wu
  • Publication number: 20210210502
    Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 8, 2021
    Inventor: Tsung-Lin Wu
  • Patent number: 10679155
    Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 9, 2020
    Assignee: Institute For Information Industry
    Inventors: Tsung-Lin Wu, Wei-Wen Wu, Yin-Jing Tien, Yi-Chang Chen, Yi-Hsin Wu, Cheng-Juei Yu
  • Patent number: 10650786
    Abstract: An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 12, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chin-Hung Lin, Wei-Chung Hung, Huai-Hao Syu, Tzu-Ping Lin, Chia-Po Chou, Tsung-Lin Wu, Han-Wei Tang, Yi-Ching Chen, Chih-Lung Lin, Ping-Fu Hsieh
  • Patent number: 10546640
    Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
  • Patent number: 10347678
    Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 9, 2019
    Assignee: Visera Technologies Company Limited
    Inventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Chin-Chuan Hsieh
  • Publication number: 20190148433
    Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Wu-Cheng KUO, Kuo-Feng LIN, Tsung-Lin WU, Chin-Chuan HSIEH
  • Publication number: 20190095827
    Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.
    Type: Application
    Filed: October 23, 2017
    Publication date: March 28, 2019
    Inventors: Tsung-Lin WU, Wei-Wen WU, Yin-Jing TIEN, Yi-Chang CHEN, Yi-Hsin WU, Cheng-Juei YU