Patents by Inventor Tsung-Lin Wu
Tsung-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250083432Abstract: A method of making a mouse pad contains: bonding and hot-press molding a body and a cloth by using a first mold and a second mold. The body is made of polyurethane (PU), the second mold includes a cavity, and a size of the cavity of the second mold is equal to a predetermined size of the body, and a guide rib surrounds the cavity. The method comprising steps of: 1) flattening the body; 2) bonding the cloth on the body; 3) cutting the body in a predetermined; 4) hot-press molding the body and the cloth; 5) sublimation printing; and 6) hot-press molding to trim the mouse pad by using the first mold and of the guide rib the second mold.Type: ApplicationFiled: July 14, 2024Publication date: March 13, 2025Inventor: Tsung-Lin Wu
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Patent number: 12009379Abstract: An image sensor is provided. The image sensor includes a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, and the first photoelectric conversion component includes: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer.Type: GrantFiled: May 1, 2017Date of Patent: June 11, 2024Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Chin-Chuan Hsieh
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Patent number: 11557598Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.Type: GrantFiled: January 11, 2022Date of Patent: January 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Tsung-Lin Wu
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Publication number: 20220130848Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventor: Tsung-Lin Wu
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Patent number: 11257837Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.Type: GrantFiled: January 20, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventor: Tsung-Lin Wu
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Publication number: 20210210502Abstract: A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.Type: ApplicationFiled: January 20, 2020Publication date: July 8, 2021Inventor: Tsung-Lin Wu
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Patent number: 10679155Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.Type: GrantFiled: October 23, 2017Date of Patent: June 9, 2020Assignee: Institute For Information IndustryInventors: Tsung-Lin Wu, Wei-Wen Wu, Yin-Jing Tien, Yi-Chang Chen, Yi-Hsin Wu, Cheng-Juei Yu
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Patent number: 10650786Abstract: An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.Type: GrantFiled: January 5, 2018Date of Patent: May 12, 2020Assignee: ASUSTEK COMPUTER INC.Inventors: Chin-Hung Lin, Wei-Chung Hung, Huai-Hao Syu, Tzu-Ping Lin, Chia-Po Chou, Tsung-Lin Wu, Han-Wei Tang, Yi-Ching Chen, Chih-Lung Lin, Ping-Fu Hsieh
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Patent number: 10546640Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.Type: GrantFiled: May 10, 2017Date of Patent: January 28, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
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Patent number: 10347678Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.Type: GrantFiled: November 16, 2017Date of Patent: July 9, 2019Assignee: Visera Technologies Company LimitedInventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Chin-Chuan Hsieh
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Publication number: 20190148433Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.Type: ApplicationFiled: November 16, 2017Publication date: May 16, 2019Inventors: Wu-Cheng KUO, Kuo-Feng LIN, Tsung-Lin WU, Chin-Chuan HSIEH
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Publication number: 20190095827Abstract: A dispatching method and system based on multiple levels of steady state production rate in working benches are provided. The dispatching method includes the following steps: receiving a plurality of real-time streaming data regarding a plurality of products being produced by a plurality of productive working benches; grouping the production rate values comprised in each real-time streaming data according to a first data binning technique, so as to produce a first steady state production rate value corresponding to each real-time streaming data; grouping the production rate values comprised in each real-time streaming data according to a second data binning technique, so as to produce a second steady state production rate value corresponding to each real-time streaming data; and determining a dispatching message of a to-be-produced product according to a portion of the first steady state production rate values and a portion of the second steady state production rate values.Type: ApplicationFiled: October 23, 2017Publication date: March 28, 2019Inventors: Tsung-Lin WU, Wei-Wen WU, Yin-Jing TIEN, Yi-Chang CHEN, Yi-Hsin WU, Cheng-Juei YU
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Publication number: 20190074314Abstract: An image sensor package includes a medium layer having a first surface and a second surface opposite to the first surface. The image sensor package also includes a metal-insulator-metal structure disposed on the first surface of the medium layer. The metal-insulator-metal structure includes a first metal layer, a first insulating layer, and a second metal layer, and the first insulating layer is disposed between the first metal layer and the second metal layer. The image sensor package further includes an optical filter disposed on the second surface of the medium layer.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Inventors: Wu-Cheng KUO, Kuo-Feng LIN, Tsung-Lin WU, Yu-Jen CHEN, Chin-Chuan HSIEH, Kuang-Peng LIN
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Patent number: 10224357Abstract: An image sensor package includes a medium layer having a first surface and a second surface opposite to the first surface. The image sensor package also includes a metal-insulator-metal structure disposed on the first surface of the medium layer. The metal-insulator-metal structure includes a first metal layer, a first insulating layer, and a second metal layer, and the first insulating layer is disposed between the first metal layer and the second metal layer. The image sensor package further includes an optical filter disposed on the second surface of the medium layer.Type: GrantFiled: September 7, 2017Date of Patent: March 5, 2019Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Yu-Jen Chen, Chin-Chuan Hsieh, Kuang-Peng Lin
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Patent number: 10134919Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.Type: GrantFiled: May 16, 2018Date of Patent: November 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventor: Tsung-Lin Wu
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Publication number: 20180315862Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.Type: ApplicationFiled: May 16, 2018Publication date: November 1, 2018Inventor: Tsung-Lin Wu
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Publication number: 20180315788Abstract: An image sensor is provided. The image sensor includes a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, and the first photoelectric conversion component includes: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer.Type: ApplicationFiled: May 1, 2017Publication date: November 1, 2018Inventors: Wu-Cheng KUO, Kuo-Feng LIN, Tsung-Lin WU, Chin-Chuan HSIEH
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Publication number: 20180276067Abstract: A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string; performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units; inputting the block information to an error checking and correcting (ECC) circuit of the memory storage device to generate a second string; and storing the second string into the rewritable non-volatile memory module.Type: ApplicationFiled: May 10, 2017Publication date: September 27, 2018Applicant: PHISON ELECTRONICS CORP.Inventors: Tsung-Lin Wu, Te-Chang Tsui, Chien-Fu Lee
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Publication number: 20180204540Abstract: An automatically brightness adjusting electronic device and a brightness adjusting method are provided. The method comprises: sensing an environmental light intensity; generating a brightness adjustment signal according to the environmental light intensity via a second control unit; and adjusting a display brightness of a display unit according to the brightness adjustment signal via a first control unit or the second control unit.Type: ApplicationFiled: January 5, 2018Publication date: July 19, 2018Inventors: CHIN-HUNG LIN, WEI-CHUNG HUNG, HUAI-HAO SYU, TZU-PING LIN, CHIA-PO CHOU, TSUNG-LIN WU, HAN-WEI TANG, YI-CHING CHEN, CHIH-LUNG LIN, PING-FU HSIEH
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Patent number: 10020404Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.Type: GrantFiled: April 27, 2017Date of Patent: July 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventor: Tsung-Lin Wu