Patents by Inventor Tsung-Ling Li

Tsung-Ling Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290715
    Abstract: A ball grid array (BGA) package for use in a touch panel controller includes a package substrate and a plurality of solder bumps. The plurality of solder bumps are disposed on the package substrate, arranged in a staggered pattern surrounding a hollow region on the package substrate, and coupled to electrodes of a touch panel via a multi-layer circuit board. The staggered pattern includes Ys1 top rows and Ys2 bottom rows, a minimum vertical distance between centers of two vertically adjacent solder bumps in the Ys1 top rows and the Ys2 bottom rows being referred to as an equivalent vertical pitch, and Ys1, Ys2 being integers exceeding 2. the hollow region has a minimum length defined by the minimum length=((Ys1?2)+(Ys2?2))*the equivalent vertical pitch.
    Type: Application
    Filed: November 20, 2022
    Publication date: September 14, 2023
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Tsung-Ling Li, Yung-Cheng Lin, Ju-Lin Huang
  • Publication number: 20230104261
    Abstract: A single inductor multiple output regulator includes an inductor, a number of capacitors, a number of switches coupled with the capacitors and a control circuit coupled with the switches and configured to apply at least two multi-switching pulses to a multi-pulse controlled one of the switches in each cycle.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Inventors: Wei-Jen CHANG, Wei-Yu CHEN, Hao-Hung LO, Tsung-Ling LI, Po-Hung CHEN
  • Publication number: 20220015164
    Abstract: An electronic device includes a first electronic element and a second electronic element. The first electronic element stores a pairing information. The second electronic element is detachably disposed on the first electronic element. When the second electronic element is electrically connected with the first electronic element, the first electronic element is wirelessly communicated with a third electronic element. When the second electronic element is detached from the first electronic element, the second electronic element is wirelessly communicated with the third electronic element through the pairing information.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 13, 2022
    Inventors: Tsung-Ling LI, Chi-Hsueh WANG
  • Publication number: 20180158598
    Abstract: An inductor equipped with imbalanced magnetic-cancelling (IMC) architecture and an associated apparatus are provided. The inductor may include a first terminal, a second terminal, and a plurality of partial wirings coupled between the first terminal and the second terminal. The plurality of partial wirings may include a first set of partial wirings coupled in series and coupled to the first terminal, a second set of partial wirings coupled in series and coupled to the second terminal, and a third set of partial wirings coupled in series and coupled between the first set of partial wirings and the second set of partial wirings. Additionally, a second area enclosed by the first set of partial wirings and the second set of partial wirings is different from a first area enclosed by the third set of partial wirings, to provide the inductor with the IMC architecture.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 7, 2018
    Inventors: Min-Chiao Chen, Tao-Yi Lee, Tsung-Ling Li
  • Patent number: 8891707
    Abstract: A receiving device includes: a mixer module arranged to receive an input signal to generate a down-converted output; a first active filter, the first active filter arranged to receive the down-converted output and perform an active filtering process upon the down-converted output to generate a first filtered output; a passive filter, the passive filter arranged to receive the first filtered output and perform a passive filtering process upon the first filtered output to generate a second filtered output; and a processing circuit, the processing circuit arranged to receive the second filtered output and process the second filtered output to generate an output signal corresponding to the input signal.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: MediaTek Inc.
    Inventors: Chi-Lun Lo, Chia-Hsin Wu, Tsung-Ling Li
  • Patent number: 8559653
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Mediatek Inc.
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Publication number: 20120076309
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 29, 2012
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Patent number: 8094836
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 10, 2012
    Assignee: Mediatek Inc.
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Patent number: 7957698
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Mediatek Inc.
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Publication number: 20110069797
    Abstract: A receiving device includes: a mixer module arranged to receive an input signal to generate a down-converted output; a first active filter, the first active filter arranged to receive the down-converted output and perform an active filtering process upon the down-converted output to generate a first filtered output; a passive filter, the passive filter arranged to receive the first filtered output and perform a passive filtering process upon the first filtered output to generate a second filtered output; and a processing circuit, the processing circuit arranged to receive the second filtered output and process the second filtered output to generate an output signal corresponding to the input signal.
    Type: Application
    Filed: April 16, 2010
    Publication date: March 24, 2011
    Inventors: Chi-Lun Lo, Chia-Hsin Wu, Tsung-Ling Li
  • Patent number: 7668517
    Abstract: The invention provides a radio frequency signal receiver with adequate gain control path to control the gain of a mixer and/or a channel selection filter, comprising a low noise amplifier for receiving and amplifying a radio frequency signal, a local oscillator (LO) for providing a LO signal, a mixer for down converting the radio frequency signal by the LO signal to an intermediate signal, a channel selection filter for receiving and filtering the intermediate signal to develop an output signal, and an automatic gain control unit for feedback adjusting the gain of the low noise amplifier and forward controlling the gain of the mixer and channel selection filter in accordance with the output signal of the low noise amplifier.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: February 23, 2010
    Assignee: Mediatek Inc.
    Inventor: Tsung-Ling Li
  • Publication number: 20090252337
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.
    Type: Application
    Filed: April 8, 2008
    Publication date: October 8, 2009
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Publication number: 20090233566
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Publication number: 20070293177
    Abstract: The invention provides a radio frequency signal receiver with adequate gain control path to control the gain of a mixer and/or a channel selection filter, comprising a low noise amplifier for receiving and amplifying a radio frequency signal, a local oscillator (LO) for providing a LO signal, a mixer for down converting the radio frequency signal by the LO signal to an intermediate signal, a channel selection filter for receiving and filtering the intermediate signal to develop an output signal, and an automatic gain control unit for feedback adjusting the gain of the low noise amplifier and forward controlling the gain of the mixer and channel selection filter in accordance with the output signal of the low noise amplifier.
    Type: Application
    Filed: October 6, 2006
    Publication date: December 20, 2007
    Applicant: MEDIATEK INC.
    Inventor: Tsung-Ling Li