Abstract: Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various display applications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived brightness level of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.

Abstract: Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various display applications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived brightness level of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.

Abstract: Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various projection applications, storage and optical communications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. These sub-image elements are driven by PWM as in digital modulation. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived effect of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.

Abstract: A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of programmable circuits for electrically connecting the input and output leads of the plurality of logic elements to each other through the group of interconnect lines. The programmable integrated circuit further comprises a test circuit having at least one input and one output. Further the programmable integrated circuit comprises a second set of programmable circuits for electrically connecting the one output of the test circuit to the plurality of input leads of each of the plurality of logic elements and for electrically connecting the at least one output lead of each of the plurality of logic elements to the one input of the test circuit, through the group of interconnect lines.

Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

Abstract: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.