Abstract: Open chain sophorolipids may be produced by fermentation with Candida sp. NRRL Y-27208 or C. riodocensis. Dimers and trimers of sophorolipids are also produced. The sophorolipds are produced by inoculating a fermentation medium comprising a carbon source and a lipid, with Candida riodocensis or Candida species NRRL Y-27208, and incubating under aerobic conditions and for a period of time effective to produce an open chain sophorolipid in the medium. The sophorolipids may be subsequently recovered from the fermentation medium.

Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method for manufacturing semiconductor devices includes providing a substrate having a first region and a second region defined thereon, and a shallow trench isolation (STI) formed in between the first region and the second region, the first region comprising a first gate structure and the second region comprising a second gate structure respectively formed therein; forming a patterned protecting layer covering at least the entire STI and the second region on the substrate; forming recesses not exposing the STI in the substrate respectively at two sides of the first gate structure; and forming an epitaxial layer in the recesses respectively, the epitaxial layer filling up the recesses.

Abstract: A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. The metal layer is then patterned to form a pad. An annealing process is performed, wherein the gas source for the annealing process includes hydrogen in a concentration of 50% to 90%.

Abstract: Itaconic acid may be produced in high yields by fermentation with a yeast, Pseudozyma antarctica NRRL Y-30980.

Abstract: The compound 7,10,12-trihydroxy-8(E)-octadecenoic acid (TOD) has been produced by bioconversion of ricinoleic acid by Pseudomonas aeruginosa PR3. TOD and derivatives thereof are useful for controlling biological organisms, such as fungi and insects.