Patents by Inventor Tsung-Ming Chen

Tsung-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250122457
    Abstract: A culturing device includes a culturing container, a transparent plate, a cover and a light emitting assembly. The culturing container includes a body portion and an opening portion. The body portion is connected to the opening portion. The opening portion has an opening. The transparent plate is disposed on the opening portion, and covers the opening. The cover is disposed on a side of the transparent plate located farthest away from the culturing container. The cover and the transparent plate together form an airflow channel therebetween. The light emitting assembly is disposed on the cover, and is located in the airflow channel.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 17, 2025
    Applicant: NATIONAL KAOHSIUNG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chi-Chang HSIEH, Tsung-Ming CHEN, Yen-Yi LI, Min-Hong CHEN
  • Patent number: 12276460
    Abstract: A modular heat exchanger includes: two finned heat sinks, each finned heat sink has multiple guiding plates and a mounting recess; a securing assembly for securing the two finned heat sinks; a heat conduction pipe mounted in the mounting recesses; multiple modular blocks linearly arranged, and each modular block has multiple inlet through holes and multiple outlet through holes; multiple water pipes, each water pipe has two ends mounted through the inlet through holes and the outlet through holes respectively; and multiple coolers mounted to an outer sidewall defined on at least one of the modular blocks. It is convenient to assemble, disassemble or expand the modular heat exchanger, so as to improve performance of the modular heat exchanger. When one of the coolers fails, it is able to reach and detach said failed cooler by disassembling some parts of the modular heat exchanger, which is convenient.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: April 15, 2025
    Inventors: Tsung-Ming Chen, Chun-Yu Chen
  • Publication number: 20250028213
    Abstract: A multicolor electrochromic device includes a substrate, a common bottom electrode layer on the substrate, a first layer having a first metal oxide on the common bottom electrode layer, a second layer having a second oxide on the common bottom electrode layer and spaced apart from the first layer, a first top electrode on the first layer, and a second top electrode on the second layer and spaced apart from the first top electrode. The second metal oxide is different from the first metal oxide. A wearable display assembly using the multicolor electrochromic device is also disclosed.
    Type: Application
    Filed: July 17, 2023
    Publication date: January 23, 2025
    Inventors: Jhih-Jian HE, Ming-Lun SHIH, Tsung-Ming CHEN
  • Publication number: 20240404924
    Abstract: A semiconductor package includes a leadframe having a die pad and lead terminals along a perimeter of the die pad, and an IC die mounted on the die pad. The IC die includes I/O pads disposed on an active front surface of the IC die. The IC die includes a semiconductor substrate, a circuit block fabricated on the semiconductor substrate, and a through substrate via (TSV) extending through a thickness of the semiconductor substrate. Bond wires extend between the I/O pads and the lead terminals, respectively. A molding compound encapsulates the IC die, the bond wires, and the leadframe.
    Type: Application
    Filed: June 3, 2024
    Publication date: December 5, 2024
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Ming Chen, Yu-Ting Chou, Keng-Chang Liang, Chiyuan Lu, Jing-Hong Conan Zhan
  • Publication number: 20240268066
    Abstract: A method for controlling fan and a heat dissipation device are provided, the heat dissipation device includes a plurality of dual-rotor fans and a boost unit. Each dual-rotor fan includes two rotor units. A first end of the boost unit is connected to the rotor units of the dual-rotor fans, a second end is connected to a power supply terminal. The heat dissipation device determines if the dual-rotor fan with one of the rotor units fails to be a target fan; controls the boost unit to increase a voltage of a power supply of the power supply terminal to a first predetermined voltage value, to output the power supply to a normal one of the rotor units of the target fan.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 8, 2024
    Inventor: TSUNG-MING CHEN
  • Publication number: 20240243769
    Abstract: A radio frequency (RF) front-end circuit of a wireless communication device is provided. The RF front-end circuit includes a receiving amplifier, a down-converter, an up-converter, a transmitting amplifier and an output driver, where the receiving amplifier and the down-converter are configured to process received signals according to a local oscillation (LO) signal, and the up-converter, the transmitting amplifier and the output driver are configured to process transmitted signals according to the LO signal. The receiving amplifier, the up-converter or the transmitting amplifier includes a transformer load. The transformer load includes a switchable inductor. When the wireless communication device operates in a first mode, the LO signal has a first frequency, and the switchable inductor has a first inductance. When the wireless communication device operates in a second mode, the LO signal has a second frequency, and the switchable inductor has a second inductance.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 18, 2024
    Applicant: MediaTek Inc.
    Inventors: Tsung-Ming Chen, Wei-Kai Hong, Ting-Wei Liang, Wei-Pang Chao, Po-Yu Chang
  • Patent number: 12028080
    Abstract: A clock generating circuit includes a control circuit and a phase interpolator. The control circuit converts an input signal to generate an encoded signal having multiple bits and adjusts arrangement of the bits according to a pointer to generate a control signal having multiple control bits. The phase interpolator includes a first driving circuit, a second driving circuit and an output terminal configured to output an interpolated clock signal. The first driving circuit receives a first clock signal and includes multiple first driving units that are turned on or off to drive the first clock signal in response to multiple first control bits in the control bits. The second driving circuit receives a second clock signal and includes multiple second driving units that are turned on or off to drive the second clock signal in response to multiple second control bits in the control bits.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: July 2, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventor: Tsung-Ming Chen
  • Publication number: 20240171204
    Abstract: A multilane transmitter includes a plurality of transmitter lane circuits and a phase lock circuit. The phase lock circuit includes an oscillating circuit. The oscillating circuit is configured to provide clock signals corresponding to the transmitter lane circuits. The oscillating circuit includes a plurality of logic units. Clock receiving terminals of the transmitter lane circuits are coupled to an output terminal of one of the plurality of logic units.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 23, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Tsung-Ming CHEN
  • Publication number: 20230253973
    Abstract: A clock generating circuit includes a control circuit and a phase interpolator. The control circuit converts an input signal to generate an encoded signal having multiple bits and adjusts arrangement of the bits according to a pointer to generate a control signal having multiple control bits. The phase interpolator includes a first driving circuit, a second driving circuit and an output terminal configured to output an interpolated clock signal. The first driving circuit receives a first clock signal and includes multiple first driving units that are turned on or off to drive the first clock signal in response to multiple first control bits in the control bits. The second driving circuit receives a second clock signal and includes multiple second driving units that are turned on or off to drive the second clock signal in response to multiple second control bits in the control bits.
    Type: Application
    Filed: January 13, 2023
    Publication date: August 10, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventor: Tsung-Ming Chen
  • Publication number: 20230175782
    Abstract: A modular heat exchanger includes: two finned heat sinks, each finned heat sink has multiple guiding plates and a mounting recess; a securing assembly for securing the two finned heat sinks; a heat conduction pipe mounted in the mounting recesses; multiple modular blocks linearly arranged, and each modular block has multiple inlet through holes and multiple outlet through holes; multiple water pipes, each water pipe has two ends mounted through the inlet through holes and the outlet through holes respectively; and multiple coolers mounted to an outer sidewall defined on at least one of the modular blocks. It is convenient to assemble, disassemble or expand the modular heat exchanger, so as to improve performance of the modular heat exchanger. When one of the coolers fails, it is able to reach and detach said failed cooler by disassembling some parts of the modular heat exchanger, which is convenient.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Tsung-Ming CHEN, Chun-Yu CHEN
  • Patent number: 11582504
    Abstract: The present invention discloses a signal output circuit applying bandwidth broadening mechanism for an image signal transmission apparatus that includes a first driving circuit and a second driving circuit. The first driving circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a first output signal, in which a zero point and two poles of a frequency response of the first driving circuit are determined by circuit parameters thereof. The second driving circuit is configured to receive and amplify the first output signal to generate a second output signal for an image receiving apparatus.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 14, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Ming Chen, Cheng-Yu Liu
  • Publication number: 20220272401
    Abstract: The present invention discloses a signal output circuit applying bandwidth broadening mechanism for an image signal transmission apparatus that includes a first driving circuit and a second driving circuit. The first driving circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a first output signal, in which a zero point and two poles of a frequency response of the first driving circuit are determined by circuit parameters thereof. The second driving circuit is configured to receive and amplify the first output signal to generate a second output signal for an image receiving apparatus.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 25, 2022
    Inventors: TSUNG-MING CHEN, CHENG-YU LIU
  • Patent number: 11228281
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 18, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Patent number: 11223363
    Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 11, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shawn Min, Yi-Jang Wu, Tsung-Ming Chen, Chieh-Yuan Hsu, Cheng-Yu Liu
  • Publication number: 20210376842
    Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.
    Type: Application
    Filed: May 21, 2021
    Publication date: December 2, 2021
    Inventors: SHAWN MIN, YI-JANG WU, TSUNG-MING CHEN, CHIEH-YUAN HSU, CHENG-YU LIU
  • Patent number: 10801636
    Abstract: An energy saving system utilizing temperature sensing flow control valve to realizing chilled water loop is provided, which includes an air blower, a temperature sensing flow control valve and a temperature setter. The air blower is disposed in the chilled water loop of a building to chill the air by the chilled water loop and then discharge the chilled air from the air outlet of the air blower. The valve is connected to a chilled water outlet beside the air blower and controls the flow of the chilled water flowing from the air blower to the chilled water loop. The temperature setter is connected to the valve and detects the temperature of the air discharged from the air outlet; the temperature setter opens or closes the temperature sensing flow control valve according to the detected air temperature and adjusts the flow of the chilled water by the valve.
    Type: Grant
    Filed: August 4, 2018
    Date of Patent: October 13, 2020
    Assignee: QUALITEK PRECISION INDUSTRIAL CO., LTD.
    Inventors: Tsung-Ming Chen, Kung-Chao Tung, Po-Cheng Tung
  • Patent number: 10763858
    Abstract: A current mode logic buffer device for suppressing electromagnetic interference includes two output ports and three or more sets of current mode logic buffers. First, second, and third current mode logic buffers respectively generate first, second, and third clock signals in response to first, second, and third differential input signals. The second differential input signal is delayed by a time difference from the first differential input signal, and the third differential input signal is delayed by the time difference from the second differential input signal. The output ports receive the first clock signal, the second clock signal, and the third clock signal, and output a full clock signal. A signal generating method for suppressing electromagnetic interference is also provided.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Tsung-Ming Chen
  • Publication number: 20200058859
    Abstract: A resistive memory device includes a first electrode, a resistance switching layer and a second electrode. The resistance switching layer is disposed on the first electrode and includes a ternary transition metal oxide. The second electrode is disposed on the resistance switching layer.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: Chao-Hung WANG, Dai-Ying LEE, Kuang-Hao CHIANG, Yu-Hsuan LIN, Tsung-Ming CHEN
  • Publication number: 20200028469
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 23, 2020
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Publication number: 20190360608
    Abstract: An energy saving system utilizing temperature sensing flow control valve to realizing chilled water loop is provided, which includes an air blower, a temperature sensing flow control valve and a temperature setter. The air blower is disposed in the chilled water loop of a building to chill the air by the chilled water loop and then discharge the chilled air from the air outlet of the air blower. The valve is connected to a chilled water outlet beside the air blower and controls the flow of the chilled water flowing from the air blower to the chilled water loop. The temperature setter is connected to the valve and detects the temperature of the air discharged from the air outlet; the temperature setter opens or closes the temperature sensing flow control valve according to the detected air temperature and adjusts the flow of the chilled water by the valve.
    Type: Application
    Filed: August 4, 2018
    Publication date: November 28, 2019
    Inventors: TSUNG-MING CHEN, KUNG-CHAO TUNG, PO-CHENG TUNG