Abstract: A cholesteric liquid crystal writing board, which can display a writing track, includes a cholesteric liquid crystal device, an optical layer, a photo-sensing array and a voltage control circuit. The cholesteric liquid crystal device includes plural liquid crystal control areas. The optical layer has plural optical openings. The photo-sensing array includes plural photo sensors arranged in an array. The photo sensors are disposed corresponding to the optical openings. One of the photo sensors senses a luminous flux change and generates an erasing signal accordingly. The voltage control circuit receives the erasing signal and outputs a voltage signal accordingly to the liquid crystal control areas corresponding to the photo sensors having the luminous flux change, such that a part or all of cholesteric liquid crystals corresponding to the liquid crystal control areas are morphologically changed so as to clear a part or all of the writing trace.

Abstract: A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a mode control unit. The photo-sensing array layer is disposed at one side of the light-emitting surface of the cholesteric liquid crystal device. The photo-sensing array layer comprises a plurality of gate control lines and a plurality of mode control lines. The mode control unit comprises a main control circuitry and a plurality of mode switches coupled to the main control circuitry. Each mode switch is coupled to one of the mode control lines correspondingly. The gate control lines intersect with the mode control lines so as to define a plurality of light sensing areas arranged in an array. Each light sensing area has a switch element and a light-sensing element. The main control circuitry controls each mode switch to be switched between a voltage output mode and a voltage write mode.

Abstract: A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a mode control unit. The photo-sensing array layer is disposed at one side of the light-emitting surface of the cholesteric liquid crystal device. The photo-sensing array layer comprises a plurality of gate control lines and a plurality of mode control lines. The mode control unit comprises a main control circuitry and a plurality of mode switches coupled to the main control circuitry. Each mode switch is coupled to one of the mode control lines correspondingly. The gate control lines intersect with the mode control lines so as to define a plurality of light sensing areas arranged in an array. Each light sensing area has a switch element and a light-sensing element. The main control circuitry controls each mode switch to be switched between a voltage output mode and a voltage write mode.

Abstract: A cholesteric liquid crystal writing board, which can display a writing track, includes a cholesteric liquid crystal device, an optical layer, a photo-sensing array and a voltage control circuit. The cholesteric liquid crystal device includes plural liquid crystal control areas. The optical layer has plural optical openings. The photo-sensing array includes plural photo sensors arranged in an array. The photo sensors are disposed corresponding to the optical openings. One of the photo sensors senses a luminous flux change and generates an erasing signal accordingly. The voltage control circuit receives the erasing signal and outputs a voltage signal accordingly to the liquid crystal control areas corresponding to the photo sensors having the luminous flux change, such that a part or all of cholesteric liquid crystals corresponding to the liquid crystal control areas are morphologically changed so as to clear a part or all of the writing trace.

Abstract: A cholesteric liquid crystal writing board can display a writing track, and comprises a cholesteric liquid crystal device, a photo-sensing array layer, a sensing-signal processing circuitry and a voltage control circuitry. The cholesteric liquid crystal device comprises a plurality of liquid crystal control areas. The photo-sensing array layer comprises a plurality of photo-sensing dot-areas arranged in an array, a photo-sensing element of the photo-sensing dot-area senses a luminous flux change and generates a sensing signal. The sensing-signal processing circuitry receives the sensing signal and accordingly outputs position data of the photo-sensing element in the photo-sensing array layer.

Abstract: A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a sensing-signal processing circuitry. The cholesteric liquid crystal device comprises a cholesteric liquid crystal layer, and has a light-entering surface and a light-emitting surface opposite to the light-entering surface. The photo-sensing array layer comprises a plurality of photo-sensing elements arranged in an array. The photo-sensing array layer is disposed on one side of the light-emitting surface of the cholesteric liquid crystal device. When at least a portion of the cholesteric liquid crystal layer is morphologically changed due to a pressure caused by a press to generate a luminous flux change, one of the photo-sensing elements of the photo-sensing array layer senses the luminous flux change and generates a sensing signal accordingly.

Abstract: A flip-chip package is described. The flip-chip package includes a chip, a substrate, supporters and electrically conductive adhesive bumps. The electrically conductive adhesive bumps are located between the chip and the substrate electrically connecting the bonding pads on the former and the bump pads on the latter, wherein each electrically conductive adhesive bump has a smaller diameter at the central portion thereof than at the end portions thereof. The supporters are also disposed between the chip and the substrate surrounding the active area of the chip, so that the chip can be supported on the substrate.

Abstract: The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package.

Abstract: A flip-chip package is described. The flip-chip package includes a chip, a substrate, supporters and electrically conductive adhesive bumps. The electrically conductive adhesive bumps are located between the chip and the substrate electrically connecting the bonding pads on the former and the bump pads on the latter, wherein each electrically conductive adhesive bump has a smaller diameter at the central portion thereof than at the end portions thereof. The supporters are also disposed between the chip and the substrate surrounding the active area of the chip, so that the chip can be supported on the substrate.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Abstract: A multichip module mainly comprises two chips disposed on a substrate in a stacking arrangement. The multichip module is characterized by having a dummy chip interposed between the two semiconductor chips. The dimension of the dummy chip is smaller than the lower semiconductor chip such that no portion of the dummy chip interferes with a vertical line of sight of each bonding pad of the lower semiconductor chip to permit wire bonding thereof. Furthermore, the dummy chip has a predetermined thickness sufficient to provide clearance between the two chips for keeping the upper chip from damaging the bonding wires coupled to the lower chip.

Abstract: The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface, of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step the cycle time may be reduced thereby cutting down the production cost.