Patents by Inventor Tsung-Shu Lin

Tsung-Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of manufacture
    Patent number: 10833030
    Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chen-Hua Yu, Tsung-Shu Lin, Wei-Cheng Wu
  • Semiconductor Package and Method of Forming the Same
    Publication number: 20200343193
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Devices employing thermal and mechanical enhanced layers and methods of forming same
    Patent number: 10811394
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Integrated Fan-Out Structure and Method of Forming
    Publication number: 20200303332
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200273828
    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Shou-Yi Wang, Tsung-Shu Lin
  • Semiconductor package and manufacturing method thereof
    Patent number: 10756038
    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Shou-Yi Wang, Tsung-Shu Lin
  • Semiconductor package and method of forming the same
    Patent number: 10714426
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Package Structure and Method and Equipment for Forming the Same
    Publication number: 20200219786
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 9, 2020
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Packaging device and method of making the same
    Patent number: 10700033
    Abstract: The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Ming-Da Cheng, Wen-Hsiung Lu, Bor-Rung Su
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200203303
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
    Type: Application
    Filed: May 13, 2019
    Publication date: June 25, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Shu Lin, Hsuan-Ning Shih
  • INTEGRATED CIRCUIT PACKAGE AND METHOD
    Publication number: 20200185304
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Application
    Filed: April 4, 2019
    Publication date: June 11, 2020
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Integrated fan-out structure and method of forming
    Patent number: 10679953
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20200135610
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: CHI-HSI WU, WENSEN HUNG, TSUNG-SHU LIN, SHIH-CHANG KU, TSUNG-YU CHEN, HUNG-CHI LI
  • SEMICONDUCTOR DEVICE AND PACKAGE ASSEMBLY INCLUDING THE SAME
    Publication number: 20200098712
    Abstract: A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 26, 2020
    Inventors: Chita CHUANG, Yao-Chun CHUANG, Tsung-Shu LIN, Chen-Cheng KUO, Chen-Shien CHEN
  • Contact Pad for Semiconductor Device
    Publication number: 20200051936
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 13, 2020
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • HEAT SPREADING DEVICE AND METHOD
    Publication number: 20200051888
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 13, 2020
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Device and Method for UBM/RDL Routing
    Publication number: 20190393195
    Abstract: An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: Meng-Tsan Lee, Wei-Cheng Wu, Tsung-Shu Lin
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10515867
    Abstract: The present disclosure provides a semiconductor structure including a substrate, a first die over the substrate, a second die over the first die, a heat spreader having a sidewall facing toward and proximal to a sidewall of the first die, and a thermal interface material (TIM) between the sidewall of the first die and the sidewall of the heat spreader. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the TIM.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20190385929
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: March 1, 2019
    Publication date: December 19, 2019
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Packaging assembly and method of making the same
    Patent number: 10483225
    Abstract: A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device further includes a conductive pillar on the UBM layer, and a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer. The packaging assembly further includes a substrate. The substrate includes a conductive region, and a mask layer overlying the substrate and exposing a portion of the conductive region. The packaging assembly further includes a joint solder structure between the conductive pillar and the conductive region.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chita Chuang, Yao-Chun Chunag, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen