Patents by Inventor Tsung-Tang TSAI
Tsung-Tang TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12249583Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: GrantFiled: August 15, 2023Date of Patent: March 11, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
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Patent number: 12216157Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: GrantFiled: August 22, 2023Date of Patent: February 4, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
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Patent number: 12040261Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: GrantFiled: March 29, 2022Date of Patent: July 16, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
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Patent number: 11894340Abstract: A package structure includes a wiring structure and a first electronic device. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The first electronic device is electrically connected to the wiring structure, and has a first surface, a second surface and at least one lateral side surface extending between the first surface and the second surface. The first electronic device includes a first active circuit region and a first protrusion portion. The first protrusion portion protrudes from the at least one lateral side surface of the first electronic device. A portion of the first active circuit region is disposed in the first protrusion portion.Type: GrantFiled: November 15, 2019Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
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Publication number: 20240021540Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: ApplicationFiled: August 15, 2023Publication date: January 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Publication number: 20230393194Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Patent number: 11733294Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: GrantFiled: March 6, 2020Date of Patent: August 22, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
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Patent number: 11728282Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: GrantFiled: October 17, 2019Date of Patent: August 15, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Min Lung Huang, Huang-Hsien Chang, Tsung-Tang Tsai, Ching-Ju Chen
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Patent number: 11631734Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.Type: GrantFiled: November 23, 2020Date of Patent: April 18, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu
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Patent number: 11428946Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.Type: GrantFiled: May 11, 2020Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
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Publication number: 20220223507Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Tsung-Tang TSAI, Huang-Hsien CHANG, Ching-Ju CHEN
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Patent number: 11289411Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: GrantFiled: July 29, 2020Date of Patent: March 29, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
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Patent number: 11257742Abstract: A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions.Type: GrantFiled: July 2, 2020Date of Patent: February 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Tsung-Tang Tsai
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Publication number: 20220005756Abstract: A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Tsung-Tang TSAI
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Publication number: 20210278457Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: March 6, 2020Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Publication number: 20210233836Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.Type: ApplicationFiled: July 29, 2020Publication date: July 29, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Tsung-Tang TSAI, Huang-Hsien CHANG, Ching-Ju CHEN
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Publication number: 20210151407Abstract: A package structure includes a wiring structure and a first electronic device. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The first electronic device is electrically connected to the wiring structure, and has a first surface, a second surface and at least one lateral side surface extending between the first surface and the second surface. The first electronic device includes a first active circuit region and a first protrusion portion. The first protrusion portion protrudes from the at least one lateral side surface of the first electronic device. A portion of the first active circuit region is disposed in the first protrusion portion.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Publication number: 20210118812Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
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Publication number: 20210104595Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.Type: ApplicationFiled: November 23, 2020Publication date: April 8, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Syu-Tang LIU, Huang-Hsien CHANG, Tsung-Tang TSAI, Hung-Jung TU
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Patent number: 10847602Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.Type: GrantFiled: January 3, 2019Date of Patent: November 24, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu