Patents by Inventor Tsung Tsai

Tsung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226339
    Abstract: An advanced semiconductor packaging structure includes a circuit board, a first chip disposed on the circuit board, and a second chip disposed on the first chip. The first chip has solder balls arranged at intervals and bonded to the circuit board, and first pads arranged at intervals. The second chip has second pads arranged at intervals. Each of the second pads is correspondingly bonded to each of the first pads. Each of the first and second pads comprises a graphene-copper composite material composed of graphene and copper. The graphene has a plurality of graphene microfilms. The graphene microfilms are dispersed and arranged in the gaps between adjacent copper atoms. The graphene microfilms have covalent bonds. Based on the total weight of the graphene-copper composite material, the graphene content is less than 3 wt %, and the oxygen content in the graphene-copper composite material is not greater than 10 ppm.
    Type: Application
    Filed: November 13, 2024
    Publication date: July 10, 2025
    Applicant: AMAZING COOL TECHNOLOGY CORPORATION
    Inventors: Hsien-Tsung Tsai, Yang-Ming Shih, Hung-Yun Hsu
  • Publication number: 20250218948
    Abstract: A semiconductor device includes a substrate, an ILD layer on the substrate, a contact electrode unit with a gate wiring layer and contacts in the ILD layer, a lower IMD layer on the ILD layer, a wiring unit with lower and upper wiring layers disposed on the lower IMD layer and connected to the contacts, interconnect units stacked along a height direction on the wiring unit, including an upper IMD layer, lower and upper wiring layers and interconnects in the upper IMD layer and connected to each other; and a bonding pad unit including an insulating layer, interconnects and an upper wiring layer in the insulating layer connected to each other. The lower wiring layer is made of a graphene-copper composite material having graphene flakes covalently bonded and dispersed between copper atoms. The graphene content is less than 3 wt % and the oxygen content is no more than 10 ppm.
    Type: Application
    Filed: September 29, 2024
    Publication date: July 3, 2025
    Applicant: AMAZING COOL TECHNOLOGY CORPORATION
    Inventors: Hsien-Tsung Tsai, Yang-Ming Shih, Hung-Yun Hsu
  • Publication number: 20250164709
    Abstract: An optical package structure is provided. The optical package structure includes a photonic integrated circuit die, an electronic integrated circuit die, an oxide layer, and a silicon carrier. The photonic integrated circuit die includes a coupler. The electronic integrated circuit die is bonded to the photonic integrated circuit die. The oxide layer is adjacent to the electronic integrated circuit die. The silicon carrier includes a first part over the electronic integrated circuit die and a second part over the oxide layer. A trench is formed in the second part of the silicon carrier.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa CHEN, Chih-Tsung TSAI
  • Publication number: 20250160007
    Abstract: A method of making a pixel includes doping a workpiece to define a photosensitive device. The method further includes etching the workpiece to define a protrusion and a bulk, wherein the protrusion is above the bulk, and the photosensitive device is in both the protrusion and the bulk. The method further includes doping the protrusion to define a protrusion doping region in the protrusion. The method further includes forming an isolation structure in the protrusion surrounding the protrusion doping region.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 15, 2025
    Inventor: Bo-Tsung TSAI
  • Patent number: 12253895
    Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: March 18, 2025
    Assignee: Realtek Semiconductor Corporation
    Inventors: Chao-Min Lai, Chien-Liang Chen, Ming-Tsung Tsai
  • Publication number: 20250084274
    Abstract: A curable composition includes an epoxy monomer component and an aniline-based hardener. The epoxy monomer component is a first component formed from a first epoxy monomer represented by Formula (I), or a second component including the first epoxy monomer represented by Formula (I) and a second epoxy monomer different from the first epoxy monomer represented by Formula (I), wherein each of the substituents in Formula (I) is given the definitions as set forth in the Specification and Claims. Based on 100 wt % of the epoxy monomer component, an amount of the first epoxy monomer represented by Formula (I) is not smaller than 25 wt % and less than 100 wt % and an amount of the second epoxy monomer is greater than 0% and not greater than 75 wt %. A cured product formed from the curable composition, and a method for encapsulating a semiconductor device using the curable composition are also provided.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 13, 2025
    Inventors: Yun-Ching WU, Yu-Lin HUANG, Ming-Tsung TSAI, Pei-Nung CHEN, Shu-Wei CHANG, Ming-Tsung HSU
  • Publication number: 20250081508
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 6, 2025
    Inventors: Yuan Tsung TSAI, Yao Jui KUO, Chia-Wei FAN, Ying Ming WANG, Shih-Hao CHEN, Ling-Sung WANG
  • Patent number: 12235313
    Abstract: A composite intermediary device using vertical probe for wafer testing, comprising: a printed circuit board, a glass interposer and a vertical probe set; wherein the printed circuit board has printed circuit connected with a measuring apparatus, the glass interposer has multiple contact pads connected with the printed circuit, and then the probes of the vertical probe set are against the contact pads of the glass interposer and the bumps of the device under test. By a fine pitch configuration of the printed circuit and the contact pads of the glass interposer, the present invention achieves the requirements of synchronous and interleaved testing of multiple ICs.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: February 25, 2025
    Assignee: SYU GUANG TECHNOLOGY CO., LTD.
    Inventors: Kun Yu Wu, Ming Tsung Tsai
  • Publication number: 20250044530
    Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized with an optical interposer. In embodiments a method patterns a substrate to form a recess with a sidewall, forms a mirror coating on the sidewall, deposits and patterns a material to form a first waveguide adjacent to the mirror coating, and bonds an optical interposer over the first waveguide.
    Type: Application
    Filed: December 1, 2023
    Publication date: February 6, 2025
    Inventors: Ming-Fa Chen, Chih-Tsung Tsai, Kuo Chin Hsu
  • Patent number: 12183767
    Abstract: A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion is above the bulk. The pixel further includes a protrusion doping region in the protrusion. The pixel further includes an isolation structure in the protrusion, wherein the isolation structure surrounds the protrusion doping region. The pixel further includes a photosensitive device, wherein the photosensitive device is in the bulk and the protrusion.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Bo-Tsung Tsai
  • Publication number: 20240404954
    Abstract: A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Tsung Tsai, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Yi-Da Tsai
  • Publication number: 20240404871
    Abstract: Methods for forming a dielectric isolation region between two active regions are disclosed herein. A mandrel is formed on a substrate, then etched to form a trench. Spacers are formed on the sidewalls of the mandrel. The mandrel is removed, and the substrate is etched to form fins extending in a first direction in the two active regions, and of fins extending in a second direction. A mask is formed that exposes the substrate between the fins extending in the second direction. The substrate is etched to form a trench. The trench is filled with a dielectric material up to the top of the fins to form the dielectric isolation region. The methods provide better depth control during etching between the two active regions, and also permit the trench to extend deeper into the substrate due to reduced depth/width ratios during the etching steps.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Wei Che Tsai, Yuan Tsung Tsai, Hsin-Yi Tsai, Ying Ming Wang, Hsien Hua Tseng, Shih-Hao Chen
  • Publication number: 20240371909
    Abstract: A method for fabricating an image sensor is provided. The method includes forming a first light-sensitive pixel unit and a second light-sensitive pixel unit neighboring the first light-sensitive pixel unit in a sensor wafer, and bonding the sensor wafer to a circuit wafer. Forming the first light-sensitive pixel unit and the second light-sensitive pixel unit includes forming a first light-sensitive element and a second light-sensitive element in the sensor wafer; and forming a first source contact over the first light-sensitive element and a second source contact over the second light-sensitive element. Bonding the sensor wafer to the circuit wafer is performed such that a first pixel circuit of the circuit wafer is electrically connected to the first source contact, and a second pixel circuit of the circuit wafer is electrically connected to the second source contact.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung TSAI
  • Publication number: 20240313026
    Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
    Type: Application
    Filed: May 26, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bo-Tsung Tsai
  • Patent number: 12080746
    Abstract: A method for fabricating an image sensor is provided. The method includes doping a bottom portion of a semiconductor substrate with a first dopant to form a light-sensitive element in the bottom portion of the semiconductor substrate; etching a top portion of the semiconductor substrate to form a post structure on the light-sensitive element; forming a gate structure on at least one sidewall of the post structure, wherein the gate structure exposes a first part of the bottom portion of the semiconductor substrate; doping the exposed first part of the bottom portion of the semiconductor substrate with a second dopant to form a pinning layer on the light-sensitive element, wherein the second dopant has a conductivity type opposite that of the first dopant; and forming a contact on the post structure.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 12074190
    Abstract: A device includes a substrate, a light sensitive element, a pinning region, a lightly-doped region, a floating node, and a gate stack. The light sensitive element is in the substrate. The pinning region is in the substrate and is over the light sensitive element. The lightly-doped region is laterally adjacent the pinning region. The floating node is in the pinning region, the floating node being spaced from and surrounded by the lightly-doped region. A first portion of the pinning region is between the floating node and the lightly-doped region. The gate stack is over the first portion of the pinning region.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bo-Tsung Tsai
  • Patent number: 12021103
    Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bo-Tsung Tsai
  • Publication number: 20240190491
    Abstract: A mobile kitchen cart assembly has a cart and two supporting stands respectively disposed at two sides of the cart. The cart includes a cart body, a cover plate, and multiple casters disposed at a bottom of the cart body. The cart body includes a carrier portion having an accommodating space and an operational portion located above the carrier portion and having an upper opening communicating with the accommodating space and a knife holder for holding knives. The cover plate covers the upper opening of the operational portion. The mobile kitchen cart assembly provides adequate operational space and a counter top at a suitable height by arrangement of the cart body with the cover plate and the two supporting stands.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 13, 2024
    Applicant: Tryking Development Corporation
    Inventor: MING-TSUNG TSAI
  • Publication number: 20240168373
    Abstract: A photoresist composition includes a mixture. The mixture includes a first photosensitive material and a second photosensitive material. The first photosensitive material is a 6-Sn oxide cluster, a 12-Sn oxide cluster or a combination thereof. The second photosensitive material has a composition being different from a composition of the first photosensitive material.
    Type: Application
    Filed: June 13, 2023
    Publication date: May 23, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
    Inventors: Jui-Hsiung LIU, Tsai-Sheng GAU, Burn Jeng LIN, Yan-Ru WU, Ting-An LIN, Han-Tsung TSAI, Po-Hsiung CHEN
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu