Patents by Inventor Tsung-Wei LU

Tsung-Wei LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076599
    Abstract: A device structure includes: an interposer including metal wiring structures and optical waveguides that are embedded in interlayer dielectric layers, wherein the interposer includes a stepped outer sidewall including an outermost vertical surface segment, a laterally-recessed sidewall segment that is laterally recessed relative to the outermost vertical surface segment, and a connecting horizontal surface segment that connects the outermost vertical surface segment and the laterally-recessed vertical sidewall segment; and a fiber access unit having a first end that is optically coupled to a subset of the optical waveguides through at least one optical glue portion that is interposed between the fiber access unit and the laterally-recessed sidewall segment of the stepped outer sidewall.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Tsung-Fu Tsai, Chao-Jen Wang, Szu-Wei Lu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250076594
    Abstract: Optical devices and methods of manufacture are presented in which a multi-tier connector is utilized to transmit and receive optical signals to and from an optical device. In embodiments a multi-tier connection unit receives optical signals from outside of an optical device, wherein the optical signals are originally in multiple levels. The multi-tier connection unit then routes the optical signals into a single level of optical components.
    Type: Application
    Filed: December 18, 2023
    Publication date: March 6, 2025
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Yi-Jan Lin, Yu-Sheng Huang, Tsung-Fu Tsai, Chao-Jen Wang, Szu-Wei Lu
  • Publication number: 20250044517
    Abstract: A package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a first end of the second waveguide is optically coupled to the first waveguide, wherein the waveguide structure is configured to be connected to an optical fiber component such that a second end of the second waveguide is optically coupled to an optical fiber of the optical fiber component.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Chao-Jen Wang, Szu-Wei Lu, Tsung-Fu Tsai, Chen-Hua Yu
  • Publication number: 20250042757
    Abstract: Hydrofluoric acid waste streams from semiconductor device manufacturing processes are collected and converted to cryolite utilizing disclosed systems and processes. The systems and processes are able to utilize hydrofluoric acid waste streams from multiple different sources. The systems and processes utilizing control delivery of reactant so that the produced cyrolite has low impurity levels and meets industry standards.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 6, 2025
    Inventors: You-Shiun LIN, Chao-Chun CHANG, Kuo-Wei CHEN, Yi-Chen LI, Tsung Lung LU
  • Patent number: 12155111
    Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Ju Yu, Shao-Lun Yang, Chun-Hung Yeh, Hong Jie Chen, Tsung-Wei Lu, Wei Shuen Kao
  • Patent number: 12027467
    Abstract: The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Shao-Lun Yang, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Publication number: 20230216174
    Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung Ju YU, Shao-Lun YANG, Chun-Hung YEH, Hong Jie CHEN, Tsung-Wei LU, Wei Shuen KAO
  • Publication number: 20220301995
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chih CHO, Chun-Hung YEH, Tsung-Wei LU
  • Publication number: 20220246533
    Abstract: The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chih CHO, Shao-Lun Yang, Chun-Hung YEH, Tsung-Wei LU
  • Patent number: D1064033
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: February 25, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Wen-Yo Lu, Matthew J. England, Chia-Song Liu, Tsung-Kai Cheng, Ming-Cheng Cheng, Oleksii Krasnoshchok, Oleksii Shekolian, Sergiy Aafanasov, Mikhail Donskoi, Chia-Wei Chan