Patents by Inventor Tsung-Wei LU

Tsung-Wei LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240249494
    Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.
    Type: Application
    Filed: September 4, 2023
    Publication date: July 25, 2024
    Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
  • Patent number: 12046561
    Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 12027467
    Abstract: The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Shao-Lun Yang, Chun-Hung Yeh, Tsung-Wei Lu
  • Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Publication number: 20230216174
    Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung Ju YU, Shao-Lun YANG, Chun-Hung YEH, Hong Jie CHEN, Tsung-Wei LU, Wei Shuen KAO
  • Publication number: 20220301995
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chih CHO, Chun-Hung YEH, Tsung-Wei LU
  • Publication number: 20220246533
    Abstract: The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chih CHO, Shao-Lun Yang, Chun-Hung YEH, Tsung-Wei LU