Patents by Inventor Tsung-Yang Hung
Tsung-Yang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094288Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, YI-NA FANG, MING-YIH WANG
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Patent number: 11852682Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.Type: GrantFiled: November 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Yi-Na Fang, Ming-Yih Wang
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Publication number: 20230273257Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.Type: ApplicationFiled: April 28, 2023Publication date: August 31, 2023Inventors: CHI-CHE WU, TSUNG-YANG HUNG, MING-YIH WANG, JIA-MING GUO
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Publication number: 20230194598Abstract: A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.Type: ApplicationFiled: February 9, 2023Publication date: June 22, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Che WU, Tsung-Yang HUNG, Ming-Yih WANG
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Patent number: 11675004Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.Type: GrantFiled: August 10, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang, Jia-Ming Guo
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Publication number: 20230070575Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, YI-NA FANG, MING-YIH WANG
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Patent number: 11579191Abstract: A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.Type: GrantFiled: September 16, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
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Publication number: 20230019641Abstract: A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.Type: ApplicationFiled: January 10, 2022Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi LIN, Tsung-Yang Hung, Ankita Patidar, Ming-Yih Wang, Sandeep Kumar Goel
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Patent number: 11500016Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.Type: GrantFiled: December 7, 2020Date of Patent: November 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Edna Fang, Ming-Yih Wang
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Publication number: 20220178998Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.Type: ApplicationFiled: December 7, 2020Publication date: June 9, 2022Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, EDNA FANG, MING-YIH WANG
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Publication number: 20210396804Abstract: A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.Type: ApplicationFiled: September 16, 2020Publication date: December 23, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Che WU, Tsung-Yang HUNG, Ming-Yih WANG
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Publication number: 20210389256Abstract: A method includes: determining a defective area in a semiconductor device of a semiconductor wafer; thinning the semiconductor wafer from a backside of the semiconductor wafer; bonding a first substrate to the backside of the semiconductor wafer, wherein the first substrate includes an opening and the defective area is exposed through the opening; and performing a test on the defective area by projecting a light beam from the backside through the opening.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
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Patent number: 11199508Abstract: A method includes: determining a defective area in a semiconductor device of a semiconductor wafer; thinning the semiconductor wafer from a backside of the semiconductor wafer; bonding a first substrate to the backside of the semiconductor wafer, wherein the first substrate includes an opening and the defective area is exposed through the opening; and performing a test on the defective area by projecting a light beam from the backside through the opening.Type: GrantFiled: June 12, 2020Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
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Publication number: 20210356521Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.Type: ApplicationFiled: August 10, 2020Publication date: November 18, 2021Inventors: CHI-CHE WU, TSUNG-YANG HUNG, MING-YIH WANG, JIA-MING GUO
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Patent number: 8237462Abstract: A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.Type: GrantFiled: August 11, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yang Hung, Aaron Wang
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Patent number: 8125235Abstract: A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.Type: GrantFiled: May 3, 2010Date of Patent: February 28, 2012Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.Inventor: Tsung-Yang Hung
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Patent number: 7894173Abstract: An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.Type: GrantFiled: September 16, 2008Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Liang Deng, Tsung-Yang Hung
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Publication number: 20110037494Abstract: A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.Type: ApplicationFiled: August 11, 2009Publication date: February 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yang Hung, Aaron Wang
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Publication number: 20100244879Abstract: A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.Type: ApplicationFiled: May 3, 2010Publication date: September 30, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Tsung-Yang Hung
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Patent number: 7786771Abstract: A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.Type: GrantFiled: May 27, 2008Date of Patent: August 31, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Tsai, Tsung-Yang Hung, Chien-Hung Chen, Min-Shueh Yuan