Patents by Inventor Tsung-Yao Chiang

Tsung-Yao Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136472
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
  • Patent number: 11630769
    Abstract: A memory controller includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is configured to control access of a flash memory device. The microprocessor is configured to obtain a number of spare blocks of the flash memory device corresponding to a first operation period, determine a write speed compensation value, determine a target write speed according to the write speed compensation value and a balance speed, and determine a target garbage collection speed according to the target write speed. The microprocessor is further configured to perform one or more write operations in response to one or more write commands received from a host device in the first operation period according to the target write speed and perform at least one garbage collection operation according to the target garbage collection speed.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Publication number: 20220222008
    Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises the steps of: grouping a plurality of blocks within the flash memory module into a plurality of groups, wherein each group comprises at least two blocks; establishing a valid page table, wherein the valid page table records indexes of the plurality of blocks and corresponding numbers of valid pages, respectively; establishing a group minimum valid page array based on the valid page table; referring to the group minimum valid page array to select a target group having a global minimum valid page, wherein the global minimum valid pages is obtained by selecting a minimum value among the minimum valid pages of the groups; searching the at least two blocks within the target group to determine a target block having the global minimum valid pages; and adding the target block into a garbage collection queue.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 14, 2022
    Inventors: Tsung-Yao Chiang, Jian-Hao Huang
  • Patent number: 11295801
    Abstract: The present invention provides a method for managing a flash memory module, wherein the method includes the steps of: grouping a plurality of blocks within the flash memory module into a plurality of groups; scanning a target block of each group, without scanning all of the blocks within the group, to determine if at least a portion of blocks of the group needs to be refreshed, wherein the group that is determined that at least the portion of blocks needs to be refreshed is marked as a marked group; only scanning at least the portion of blocks of the marked group, without scanning the groups that is not marked, to determine which block needs to be refreshed, wherein the block that is determined to be refreshed is marked as a marked block; refreshing the marked block(s) by moving valid data of the marked block(s) to at least one blank block.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 5, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Publication number: 20220093168
    Abstract: The present invention provides a method for managing a flash memory module, wherein the method includes the steps of: grouping a plurality of blocks within the flash memory module into a plurality of groups; scanning a target block of each group, without scanning all of the blocks within the group, to determine if at least a portion of blocks of the group needs to be refreshed, wherein the group that is determined that at least the portion of blocks needs to be refreshed is marked as a marked group; only scanning at least the portion of blocks of the marked group, without scanning the groups that is not marked, to determine which block needs to be refreshed, wherein the block that is determined to be refreshed is marked as a marked block; refreshing the marked block(s) by moving valid data of the marked block(s) to at least one blank block.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Inventor: Tsung-Yao Chiang
  • Publication number: 20220035736
    Abstract: A memory controller includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is configured to control access of a flash memory device. The microprocessor is configured to obtain a number of spare blocks of the flash memory device corresponding to a first operation period, determine a write speed compensation value, determine a target write speed according to the write speed compensation value and a balance speed, and determine a target garbage collection speed according to the target write speed. The microprocessor is further configured to perform one or more write operations in response to one or more write commands received from a host device in the first operation period according to the target write speed and perform at least one garbage collection operation according to the target garbage collection speed.
    Type: Application
    Filed: June 8, 2021
    Publication date: February 3, 2022
    Inventor: Tsung-Yao Chiang
  • Patent number: 10824366
    Abstract: A method for recording a duration of use of a data block is disclosed, as well as a data storage device implementing that method. The data block is either an in-use data block or an empty data block. The method includes steps of: receiving and writing data into one of the in-use data blocks and writing a program time and a time interval of the data into the in-use data block. Wherein the time interval is a difference between the program time and an initial program time of the in-use data block, and the initial program time was recorded when the in-use data block wrote a first piece of data.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: November 3, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Po-Sheng Chou, Tsung-Yao Chiang
  • Patent number: 10509697
    Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of blocks, and each of the blocks includes a plurality of pages. The controller divides the pages of the blocks into a plurality of super pages which include a plurality of first pages and a plurality of second pages. The controller writes at least one super page data to one of the first pages, generates a parity code based on the at least one super page data, and stores the parity code on the random-access memory.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 17, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Publication number: 20190065309
    Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of blocks, and each of the blocks includes a plurality of pages. The controller divides the pages of the blocks into a plurality of super pages which include a plurality of first pages and a plurality of second pages. The controller writes at least one super page data to one of the first pages, generates a parity code based on the at least one super page data, and stores the parity code on the random-access memory.
    Type: Application
    Filed: May 1, 2018
    Publication date: February 28, 2019
    Inventor: Tsung-Yao Chiang
  • Patent number: 10025526
    Abstract: A storage device includes a data storage medium having a plurality of data blocks and a control unit electrically coupled to the data storage medium. The control unit is configured to access data in the data blocks, perform data reading operations to obtain a plurality of data characteristic parameters of the data blocks, obtain a first value and a second value according to the data characteristic parameters, perform an additional data reading operation on a target block selected from the data blocks to obtain an additional data characteristic parameter of the target block, and determine whether to perform a data swap operation on the target block according to the data characteristic parameter of the target block, the first value and the second value. A data moving method for the storage device is also provided.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: July 17, 2018
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Publication number: 20170286012
    Abstract: A method for recording a duration of use of a data block is disclosed, as well as a data storage device implementing that method. The data block is either an in-use data block or an empty data block. The method includes steps of: receiving and writing data into one of the in-use data blocks and writing a program time and a time interval of the data into the in-use data block. Wherein the time interval is a difference between the program time and an initial program time of the in-use data block, and the initial program time was recorded when the in-use data block wrote a first piece of data.
    Type: Application
    Filed: July 25, 2016
    Publication date: October 5, 2017
    Inventors: Po-Sheng Chou, Tsung-Yao Chiang
  • Publication number: 20170262218
    Abstract: A storage device includes a data storage medium having a plurality of data blocks and a control unit electrically coupled to the data storage medium. The control unit is configured to access data in the data blocks, perform data reading operations to obtain a plurality of data characteristic parameters of the data blocks, obtain a first value and a second value according to the data characteristic parameters, perform an additional data reading operation on a target block selected from the data blocks to obtain an additional data characteristic parameter of the target block, and determine whether to perform a data swap operation on the target block according to the data characteristic parameter of the target block, the first value and the second value. A data moving method for the storage device is also provided.
    Type: Application
    Filed: January 2, 2017
    Publication date: September 14, 2017
    Inventor: Tsung-Yao Chiang