Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.

Abstract: A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Abstract: A bonding pad that has low parasitic capacitance and that transmits little or no stress to the underlying metal layer during bonding, along with a process for manufacturing it, is described. A key feature of this structure is that the damascene wiring directly below the bonding pad has been limited to its outer edges, that is it is formed in the shape of a hollow square. This limits overlap by the aluminum pad of the damascene wiring to the via hole area only. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, it is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. A via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.

Abstract: A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Abstract: The present invention discloses an integrated method for I/O redistribution and in-situ passive components fabrication such that passive components such as resistors and capacitors can be formed simultaneously during the I/O redistribution process. Only minor modifications in the I/O redistribution process need to be made for accomplishing the present invention method. In the method, an adhesion layer formed of a high resistance material such as TiW, TiN, NiCr,or NiV can be used to connect between connective traces and to function as passive resistors. Passive capacitors can be formed by the additional deposition steps of a dielectric layer and a conductive metal layer on top of an existing connective trace formed on a bonding pad.

Abstract: A method for simultaneous bumping/bonding an IC chip to a semiconductor substrate and a semiconductor package fabricated by the method are described. In the method, a plurality of edge-type conductive pads formed of under-bump-metallurgy layers are first fabricated on an IC chip by dicing through conductive pads formed on a silicon wafer. The edge-type conductive pads, or UBM layer, are then positioned in close proximity to conductive elements formed on a top surface of a semiconductor substrate. A volume of solder is then applied to the interface between the conductive pads and the conductive elements to form electrical bonds between the two. A suitable method for applying the volume of solder may be a solder jetting technique, a solder printing technique or a method utilizing pre-applied solder paste on the surfaces to be bonded together.

Abstract: The present invention discloses a method for forming a wafer level package by first providing a silicon wafer that has a multiplicity of IC dies formed on a top surface, each of the IC dies has at least one peripheral I/O pad formed in an insulating layer, then forming at least one via plug of a conductive metal with a top surface exposed on the at least one peripheral I/O pad, then coating a layer of an insulating material that has sufficient elasticity on the surface of the wafer prior to the deposition and forming of a metal trace on the elastic material layer, at least one area array I/O pad is then formed at an opposite end of the metal trace with a solder bump formed on the I/O pad before they are reflowed into a solder ball. The elastic material layer deposited under the metal traces acts as a stress-buffing layer such that an IC circuit of high reliability can be produced on a wafer level for the low cost fabrication of IC assembly.

Abstract: A low cost method for forming an integrated resistor capacitor combination using only three masks and three mask exposure steps is described. A layer of resistor material is formed on a substrate and patterned forming a resistor and a first capacitor plate. A photoresist mask is then formed covering the resistor and a contact region of the first capacitor plate. The substrate is then immersed in an anodization solution and that part of the first capacitor plate not covered by the photoresist mask is anodized forming a capacitor dielectric. The photoresist mask is then stripped. A layer of conductor material is then formed and patterned to form contacts to the resistor, a contact to the first capacitor plate, and a second capacitor plate.