Patents by Inventor Tsung-Yeh Wu

Tsung-Yeh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087955
    Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Yi XU, Xianyuan ZHAO, Zhimin QI, Aixi ZHANG, Geraldine VASQUEZ, Dien-Yeh WU, Wei LEI, Xingyao GAO, Shirish PETHE, Wenting HOU, Chao DU, Tsung-Han YANG, Kyoung-Ho BU, Chen-Han LIN, Jallepally RAVI, Yu LEI, Rongjun WANG, Xianmin TANG
  • Patent number: 10444622
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10387602
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Publication number: 20190250503
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Publication number: 20190228127
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Patent number: 9009633
    Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsung-Yeh Wu, Chin-Lung Lin, Yao-Jen Fan, Wei-Han Chien, Chia-Chun Tsai
  • Publication number: 20140331191
    Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Tsung-Yeh Wu, Chin-Lung Lin, Yao-Jen Fan, Wei-Han Chien, Chia-Chun Tsai