Abstract: Aspects of the invention include techniques for improving the accuracy of access-limited neural network inference in low-voltage regimes. A non-limiting example method includes training a first machine learning model to perform input transformation for reducing low-voltage bit errors for a deep neural network operating in a low-voltage regime. The training includes inputting training data into the first machine learning model such that, in response, the first machine learning model produces transformed training data; inputting the transformed training data into a clean machine learning model and into perturbed machine learning models, the perturbed machine learning models being generated by applying random bit errors to the clean machine learning model; and optimizing the first machine learning model based on a comparison of output of the clean machine learning model and of the perturbed machine learning models compared to groundtruth labels for the training data.

Abstract: Techniques regarding generating a synthetic dataset of objects are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a defining component that can define a tractable forward process associated with a diffusion model, with defining the tractable forward process including inputting noise to compromise training data, resulting in compromised training data. The computer executable components can further include a training component that, using the compromised training data, trains the diffusion model to reverse process the tractable forward process, wherein the training results in a compromised diffusion model.

Abstract: Some embodiments of the present disclosure are directed to systems, computer-readable media, and computer-implemented methods for neural network training. Some embodiments are directed to determining an attack order schedule for the data sample that includes a plurality of adversarial perturbation attacks associated with the data sample, and performing a composite adversarial attack process against the data set using the determined attack order schedule to generate a perturbed data sample for the data sample. Other embodiments may be disclosed or claimed.

Abstract: Some embodiments of the present disclosure are directed to systems, computer-readable media, and computer-implemented methods for neural network calibration. Some embodiments are directed to determining a universal perturbation value and temperature scaling parameter based on a training data set, and processing a testing data set using a neural network by applying the universal perturbation value to the testing data set, and applying the temperature scaling parameter to a plurality of logits determined by the neural network based on the testing data set. Other embodiments may be disclosed or claimed.

Abstract: Transfer learning in machine learning can include receiving a machine learning model. Target domain training data for reprogramming the machine learning model using transfer learning can be received. The target domain training data can be transformed by performing a transformation function on the target domain training data. Output labels of the machine learning model can be mapped to target labels associated with the target domain training data. The transformation function can be trained by optimizing a parameter of the transformation function. The machine learning model can be reprogrammed based on input data transformed by the transformation function and a mapping of the output labels to target labels.

Abstract: Transfer learning in machine learning can include receiving a machine learning model. Target domain training data for reprogramming the machine learning model using transfer learning can be received. The target domain training data can be transformed by performing a transformation function on the target domain training data. Output labels of the machine learning model can be mapped to target labels associated with the target domain training data. The transformation function can be trained by optimizing a parameter of the transformation function. The machine learning model can be reprogrammed based on input data transformed by the transformation function and a mapping of the output labels to target labels.

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

Abstract: A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.

Abstract: A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.

Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.