Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Abstract: Techniques for protecting universal serial bus (USB) Type-C dual-role power ports in computing systems are described. In an example, a first USB Type-C dual-role power port of a computing system is enabled to sink current from a high voltage external device to a power supply of the computing system. The current is transferred through a high voltage path from the first USB Type-C dual-role power port to the power supply. Simultaneously, a high voltage path from the power supply to a second USB Type-C dual-role power port of the computing system is disabled.

Abstract: Techniques for protecting universal serial bus (USB) Type-C dual-role power ports in computing systems are described. In an example, a first USB Type-C dual-role power port of a computing system is enabled to sink current from a high voltage external device to a power supply of the computing system. The current is transferred through a high voltage path from the first USB Type-C dual-role power port to the power supply. Simultaneously, a high voltage path from the power supply to a second USB Type-C dual-role power port of the computing system is disabled.

Abstract: The present disclosure relates to circuit protection within an information handling system and a media resource unit. In one form, an information handling system can include a first external input power port and an information handling system docking interface operable to be coupled to a media resource unit interface of a media resource unit. The media resource unit can include a second external input power port. The information handling system can also include a protection circuit including a first terminal and a second terminal. The first terminal can be coupled to the first external power port and operable to receive input power from the second external power port of the media resource unit. The second terminal can be coupled to the information handling system docking interface and operable to output protected power to the media resource unit interface.

Abstract: The present disclosure relates to circuit protection within an information handling system and a media resource unit. In one form, an information handling system can include a first external input power port and an information handling system docking interface operable to be coupled to a media resource unit interface of a media resource unit. The media resource unit can include a second external input power port. The information handling system can also include a protection circuit including a first terminal and a second terminal. The first terminal can be coupled to the first external power port and operable to receive input power from the second external power port of the media resource unit. The second terminal can be coupled to the information handling system docking interface and operable to output protected power to the media resource unit interface.