Patents by Inventor Tsung-Yi Wu

Tsung-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379535
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Patent number: 12142560
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240371765
    Abstract: The present disclosure, in some embodiments, relates to a method for generating a scaled integrated chip design. The method includes forming an original integrated chip (IC) design including a graphical representation of a layout corresponding to an integrated chip to be formed on a semiconductor substrate. The original IC design includes a gate contact layer having a plurality of gate contacts and a first interconnect layer having a first plurality of interconnects. The gate contact layer is scaled at a first scaling ratio, and the first interconnect layer is scaled at a second scaling ratio that is different than the first scaling ratio.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu, Chun-Yi Lee
  • Publication number: 20240340655
    Abstract: A user equipment (UE) measures one or more reference signals received from a base station to estimate a set of parameters that characterize a wireless channel between the UE and the base station. The set of parameters includes at least a respective departure angle associated with each path of a plurality of paths of the wireless channel. The UE transmits the set of parameters to the base station to enable the base station to facilitate beamforming strategies to enhance signal quality at the UE based on at least one of a channel matrix and a transmit covariance matrix associated with the wireless channel. The channel matrix and transmit covariance matrix are represented by the set of parameters.
    Type: Application
    Filed: March 8, 2024
    Publication date: October 10, 2024
    Inventors: TSUNG-WEI CHIANG, HSUAN-YI WU, Jiann-Ching Guey, Chien-Hwa Hwang
  • Publication number: 20240249494
    Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.
    Type: Application
    Filed: September 4, 2023
    Publication date: July 25, 2024
    Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
  • Publication number: 20240241155
    Abstract: A probe card includes a structure stiffener unit including a base with a lower surface where central and peripheral supporting elements protrude out and a main circuit board is fixed, a space transformer and a probe head disposed thereunder, which are disposed to the supporting elements by bolts and defined with central and peripheral regions located correspondingly to the central and peripheral supporting elements respectively, and a metal supporting member fixed on the space transformer in a direct contact manner and located correspondingly to the central region. The supporting member has a lower surface coplanar with the lower end surface of the peripheral supporting element, which is abutted on the space transformer, and an upper surface against which the central supporting element is abutted. The space transformer has great structural strength, flatness and heat dissipation effect for satisfying the large-area requirement and great electrical property testing stability.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 18, 2024
    Applicant: MPI CORPORATION
    Inventors: CHIN-YI LIN, CHE-WEI LIN, HSUEH-CHIH WU, TSUNG-YI CHEN, SHANG-JUNG HSIEH, SHENG-YU LIN, CHIEN-KAI HUNG, SHENG-WEI LIN, SHU-JUI CHANG
  • Patent number: 12040561
    Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: July 16, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Tse-Hsuan Wang, Chien-Yi Wu, Chih-Fu Chang, Chao-Hsu Wu, Chih-Yi Chiu, Wei-Han Yen, Tsung-Chi Tsai, Shih-Keng Huang, I-Shu Lee
  • Patent number: 9465579
    Abstract: Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 11, 2016
    Assignee: National Chiao Tung University
    Inventors: Chih-Wei Liu, Shin-Kai Chen, Kuo-Chiang Chang, Tsung-Yi Wu, An-Chi Tsai
  • Publication number: 20150261500
    Abstract: Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chih-Wei Liu, Shin-Kai Chen, Kuo-Chiang Chang, Tsung-Yi Wu, An-Chi Tsai
  • Patent number: 8956920
    Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Tsung Yi Wu, Chyi Keh Chern, Tsung Wen Chang
  • Publication number: 20130319744
    Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: NXP B.V.
    Inventors: Tsung Yi Wu, Chyi Keh Chern, Tsung Wen Chang
  • Patent number: 7795923
    Abstract: A logic circuit includes first, second, third and fourth transistors. The first transistor is a first type, and has a gate terminal for receiving a control signal representative of one of NAND and NOR operations of at least first and second signals, a first terminal coupled to a first power source, and a second terminal serving as an output terminal of the logic circuit. The second transistor is a second type, and has a first terminal for receiving a third signal, and gate and second terminals respectively coupled to the gate and second terminals of the first transistor. Each of the third and fourth transistors is the first type and has a gate terminal. The gate terminals of the third and fourth transistors are respectively adapted to receive the first and second signals. The series-connected third and fourth transistors are connected in parallel to the second transistor.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: September 14, 2010
    Assignee: National Changhua University of Education
    Inventor: Tsung-Yi Wu
  • Publication number: 20070010338
    Abstract: A driving mechanism of baby rocking chair includes a transmission system having a transmission motor, a monitoring device, and a control circuit. When the rocking chair oscillates upward and approaches a predetermined set-up high point position that is affected by the gravitational force causing the slowing down of rotating speed, the monitoring device transmits a signal and provides the control circuit with the signal. As the rocking chair reaches the predetermined set-up high point position, the control circuit is capable of switching the direction of the rotation of the transmission motor. It is by this way of controlling the rotating shaft of oscillation of the rocking chair that the control circuit is capable of driving the rocking chair steadily.
    Type: Application
    Filed: May 11, 2006
    Publication date: January 11, 2007
    Inventors: Tse-Chien Wu, Ho-Sheng Chen, Tsung-Yi Wu, Yi-Chen Chen, Hui-Ju Sun
  • Publication number: 20050071144
    Abstract: A method for modeling a memory with delay back annotation in accordance with the VITAL application specific integrated circuit modeling specification begins with modeling the memory with a timing generic and a port declaration. The wire delay of the memory is then modeled, followed by modeling a timing check for the memory. The wire delay of the model of the memory is then created. A description of the functional operation of the memory is then generated. The path delay for the address, control, and data bus signals to the memory is formed by overloading the VITAL path delay procedures. The VITAL timing check procedures are overloaded to determine timing constraint violations of the timing bus signals of the memory. The VITAL wire delay procedures are overloaded to determine interconnection delay bus signals of the memory.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 31, 2005
    Inventors: Nai-Yin Sung, Tsung-Yi Wu
  • Patent number: 6424583
    Abstract: A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Nai-Yin Sung, Tsung-Yi Wu, Meng-Fan Chang, Hsien-Te Chen
  • Publication number: 20020075740
    Abstract: A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.
    Type: Application
    Filed: November 30, 2000
    Publication date: June 20, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Yin Sung, Tsung-Yi Wu, Meng-Fan Chang, Hsien-Te Chen