Patents by Inventor Tsung-Ying Tsai

Tsung-Ying Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240319573
    Abstract: A projection device includes a housing, and a light source module, an optical engine module, a liquid cooling module, a first fan group and a projection lens disposed in an accommodating space. A light emitting side plate, an air outlet side plate, and a first and a second side plate surround the accommodating space. The air outlet side plate has an air outlet, and at least one of the light emitting side plate, and the first and the second side plate has at least one air inlet. The liquid cooling module includes a heat exchanger. The first fan group is located between the heat exchanger and the air outlet. An orthographic projection area of the cooling fin set of the heat exchanger on the air outlet side plate is smaller than or equal to an orthographic projection area of the first fan group on the air outlet side plate.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 26, 2024
    Applicant: Coretronic Corporation
    Inventors: Te-Ying Tsai, Jia-Hong Dai, Tsung-Han Lin, Shao-Peng Su, Po-Hao Su
  • Publication number: 20240165730
    Abstract: The present disclosure provides a welding method, which comprise the following steps: setting up a laser welding head of a laser welding machine to perform a welding operation in a manner of swing or rotating, so that a swing path of the laser welding head relative to a processing direction of the laser welding head is defined with a deceleration zone and an acceleration zone, such that the laser welding head reduces a relative swing speed or feeding speed in the acceleration zone to avoid an undercutting occurred in a welding path of the welding process.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 23, 2024
    Inventors: Tsung-Ying TSAI, Kuang-Yao HUANG, Shih-Kai CHIEN
  • Publication number: 20240145878
    Abstract: An electrode structure of rechargeable battery includes a battery tab stack, an electrode lead, a welding protective layer and a welding seam. The battery tab stack is formed by extension of a plurality of electrode sheets. The electrode lead is joined to one side of the battery tab stack. The welding protective layer is joined to another side of the battery tab stack opposite to the electrode lead. The welding seam extends from the welding protective layer to the electrode lead through the battery tab stack.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kun-Tso CHEN, Tsung-Ying TSAI, Tsai-Chun LEE, Chih-Wei CHIEN, Hui-Ta CHENG
  • Patent number: 11800702
    Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 24, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Patent number: 11660706
    Abstract: A welding quality detection system and a welding quality detection method are provided. A detection device applies a force to at least one weld point of a first welded object or a second welded object that are welded together. A displacement detector detects a displacement signal that varies with the force or time between the first welded object and the second welded object based on the force. A detection module receives or records the displacement signal and determines whether a gap exists between the first welded object and the second welded object based on a slope of the displacement signal, so as to detect the welding quality of the weld point quickly and precisely.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 30, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Ying Tsai, Kun-Tso Chen, Chih-Wei Chien, Chung-Hsin Hsiao
  • Patent number: 11508614
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 22, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 11256139
    Abstract: A support pin supporting at least one optical component in an optical cavity includes a supporting base and a supporting section connecting the supporting base. The supporting section is made of a light-transmitting material. A plurality of grooves are integrally formed on the supporting section. The grooves reflect or refract part of incident light transmitted inside the supporting section diffusely and do not penetrate the supporting section. In addition, a backlight module and a display device with the support pins are also disclosed herein.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 22, 2022
    Assignee: AmTRAN Technology Co., Ltd.
    Inventor: Tsung-Ying Tsai
  • Publication number: 20210349351
    Abstract: A support pin supporting at least one optical component in an optical cavity includes a supporting base and a supporting section connecting the supporting base. The supporting section is made of a light-transmitting material. A plurality of grooves are integrally formed on the supporting section. The grooves reflect or refract part of incident light transmitted inside the supporting section diffusely and do not penetrate the supporting section. In addition, a backlight module and a display device with the support pins are also disclosed herein.
    Type: Application
    Filed: December 14, 2020
    Publication date: November 11, 2021
    Inventor: Tsung-Ying TSAI
  • Publication number: 20210202492
    Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 1, 2021
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Publication number: 20210146483
    Abstract: A welding quality detection system and a welding quality detection method are provided. A detection device applies a force to at least one weld point of a first welded object or a second welded object that are welded together. A displacement detector detects a displacement signal that varies with the force or time between the first welded object and the second welded object based on the force. A detection module receives or records the displacement signal and determines whether a gap exists between the first welded object and the second welded object based on a slope of the displacement signal, so as to detect the welding quality of the weld point quickly and precisely.
    Type: Application
    Filed: December 23, 2019
    Publication date: May 20, 2021
    Inventors: Tsung-Ying Tsai, Kun-Tso Chen, Chih-Wei Chien, Chung-Hsin Hsiao
  • Patent number: 10985166
    Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Publication number: 20210043684
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 10854676
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 10763260
    Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20190189620
    Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Patent number: 10276650
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20190115352
    Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 18, 2019
    Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
  • Patent number: 10249510
    Abstract: An etching method including the following steps is provided. A substrate is provided first. A first region and a second region adjacent to the first region are defined on the substrate. A material layer is formed on the substrate. A pattern mask is formed on the material layer. The patterned mask includes a first part covering the material layer on the first region and a second part including a lattice structure. The lattice structure includes a plurality of openings and a plurality of shielding parts. Each opening exposes a part of the material layer on the second region. Each shielding part is located between the openings adjacent to one another. Each shielding part covers a part of the material layer on the second region. An isotropic etching process is then performed to remove the material layer exposed by the openings and the material layer covered by the shielding parts.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 2, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Yu-Chieh Lin, Tsung-Ying Tsai, Chien-Ting Ho