Patents by Inventor Tsung-Ying Tsai
Tsung-Ying Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240319573Abstract: A projection device includes a housing, and a light source module, an optical engine module, a liquid cooling module, a first fan group and a projection lens disposed in an accommodating space. A light emitting side plate, an air outlet side plate, and a first and a second side plate surround the accommodating space. The air outlet side plate has an air outlet, and at least one of the light emitting side plate, and the first and the second side plate has at least one air inlet. The liquid cooling module includes a heat exchanger. The first fan group is located between the heat exchanger and the air outlet. An orthographic projection area of the cooling fin set of the heat exchanger on the air outlet side plate is smaller than or equal to an orthographic projection area of the first fan group on the air outlet side plate.Type: ApplicationFiled: March 21, 2024Publication date: September 26, 2024Applicant: Coretronic CorporationInventors: Te-Ying Tsai, Jia-Hong Dai, Tsung-Han Lin, Shao-Peng Su, Po-Hao Su
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Publication number: 20240165730Abstract: The present disclosure provides a welding method, which comprise the following steps: setting up a laser welding head of a laser welding machine to perform a welding operation in a manner of swing or rotating, so that a swing path of the laser welding head relative to a processing direction of the laser welding head is defined with a deceleration zone and an acceleration zone, such that the laser welding head reduces a relative swing speed or feeding speed in the acceleration zone to avoid an undercutting occurred in a welding path of the welding process.Type: ApplicationFiled: January 5, 2023Publication date: May 23, 2024Inventors: Tsung-Ying TSAI, Kuang-Yao HUANG, Shih-Kai CHIEN
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Publication number: 20240145878Abstract: An electrode structure of rechargeable battery includes a battery tab stack, an electrode lead, a welding protective layer and a welding seam. The battery tab stack is formed by extension of a plurality of electrode sheets. The electrode lead is joined to one side of the battery tab stack. The welding protective layer is joined to another side of the battery tab stack opposite to the electrode lead. The welding seam extends from the welding protective layer to the electrode lead through the battery tab stack.Type: ApplicationFiled: November 29, 2022Publication date: May 2, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kun-Tso CHEN, Tsung-Ying TSAI, Tsai-Chun LEE, Chih-Wei CHIEN, Hui-Ta CHENG
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Patent number: 11800702Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: GrantFiled: March 16, 2021Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 11660706Abstract: A welding quality detection system and a welding quality detection method are provided. A detection device applies a force to at least one weld point of a first welded object or a second welded object that are welded together. A displacement detector detects a displacement signal that varies with the force or time between the first welded object and the second welded object based on the force. A detection module receives or records the displacement signal and determines whether a gap exists between the first welded object and the second welded object based on a slope of the displacement signal, so as to detect the welding quality of the weld point quickly and precisely.Type: GrantFiled: December 23, 2019Date of Patent: May 30, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Ying Tsai, Kun-Tso Chen, Chih-Wei Chien, Chung-Hsin Hsiao
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Patent number: 11508614Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.Type: GrantFiled: October 28, 2020Date of Patent: November 22, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
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Patent number: 11256139Abstract: A support pin supporting at least one optical component in an optical cavity includes a supporting base and a supporting section connecting the supporting base. The supporting section is made of a light-transmitting material. A plurality of grooves are integrally formed on the supporting section. The grooves reflect or refract part of incident light transmitted inside the supporting section diffusely and do not penetrate the supporting section. In addition, a backlight module and a display device with the support pins are also disclosed herein.Type: GrantFiled: December 14, 2020Date of Patent: February 22, 2022Assignee: AmTRAN Technology Co., Ltd.Inventor: Tsung-Ying Tsai
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Publication number: 20210349351Abstract: A support pin supporting at least one optical component in an optical cavity includes a supporting base and a supporting section connecting the supporting base. The supporting section is made of a light-transmitting material. A plurality of grooves are integrally formed on the supporting section. The grooves reflect or refract part of incident light transmitted inside the supporting section diffusely and do not penetrate the supporting section. In addition, a backlight module and a display device with the support pins are also disclosed herein.Type: ApplicationFiled: December 14, 2020Publication date: November 11, 2021Inventor: Tsung-Ying TSAI
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Publication number: 20210202492Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Publication number: 20210146483Abstract: A welding quality detection system and a welding quality detection method are provided. A detection device applies a force to at least one weld point of a first welded object or a second welded object that are welded together. A displacement detector detects a displacement signal that varies with the force or time between the first welded object and the second welded object based on the force. A detection module receives or records the displacement signal and determines whether a gap exists between the first welded object and the second welded object based on a slope of the displacement signal, so as to detect the welding quality of the weld point quickly and precisely.Type: ApplicationFiled: December 23, 2019Publication date: May 20, 2021Inventors: Tsung-Ying Tsai, Kun-Tso Chen, Chih-Wei Chien, Chung-Hsin Hsiao
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Patent number: 10985166Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.Type: GrantFiled: October 31, 2018Date of Patent: April 20, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Publication number: 20210043684Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
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Patent number: 10854676Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.Type: GrantFiled: January 18, 2018Date of Patent: December 1, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
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Patent number: 10763260Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.Type: GrantFiled: December 11, 2018Date of Patent: September 1, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
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Patent number: 10672864Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 11, 2019Date of Patent: June 2, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20190206982Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20190189620Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.Type: ApplicationFiled: October 31, 2018Publication date: June 20, 2019Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 10276650Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 21, 2018Date of Patent: April 30, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20190115352Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.Type: ApplicationFiled: December 11, 2018Publication date: April 18, 2019Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
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Patent number: 10249510Abstract: An etching method including the following steps is provided. A substrate is provided first. A first region and a second region adjacent to the first region are defined on the substrate. A material layer is formed on the substrate. A pattern mask is formed on the material layer. The patterned mask includes a first part covering the material layer on the first region and a second part including a lattice structure. The lattice structure includes a plurality of openings and a plurality of shielding parts. Each opening exposes a part of the material layer on the second region. Each shielding part is located between the openings adjacent to one another. Each shielding part covers a part of the material layer on the second region. An isotropic etching process is then performed to remove the material layer exposed by the openings and the material layer covered by the shielding parts.Type: GrantFiled: February 28, 2018Date of Patent: April 2, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Wei Feng, Ying-Chiao Wang, Yu-Chieh Lin, Tsung-Ying Tsai, Chien-Ting Ho