Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

Abstract: A method for converting network packets and a circuit system are provided. The circuit system uses firmware therein to record tables for implementing packet conversion between two types of networks (IPv4 and IPv6). In the method, a process of mapping of address and port using encapsulation (MAP-E) or a process of mapping of address and port using translation (MAP-T) is determined according to IPv4 packets routing requirement to embody an uplink and a downlink packet conversion process. A content table stores an IPv6 packet header after the MAP-E or MAP-T process. A control table is referred to for controlling the fields to be updated when adding the IPv6 packet header. A forwarding mapping rule table is referred to for determining to convert a destination IP address of an uplink IPv6 packet, or both a source IP address and a destination IP address of a downlink IPv4 packet.

Abstract: A method of preparing selective catalytic reduction composite catalyst is provided. First, first metal compound support, second metal compound, third metal compound and water are mixed to formed a precursor solution. Then, dried mixture powder is formed from the precursor solution by a spray-drying process. Thereafter, a calcination process is performed on the dried mixture powder.

Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.

Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.

Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.

Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.

Abstract: A semiconductor device and fabricating method thereof are provided. In the fabricating method, two trenches are formed in the substrate and, then the first dielectric layers is formed on the sidewalls of the trenches and a source/drain layer is formed in each trench. A second dielectric layer is formed on the substrate and the source/drain layer. Finally, a gate structure is formed on the second dielectric layer. The source/drain layers and the first dielectric layers are placed in trenches; therefore, device dimension can be reduced.