Patents by Inventor Tsung-Yu Lee

Tsung-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076151
    Abstract: A device for detecting optical loss includes a first light-guiding cable, a second light-guiding cable, a light detector, at least one angle-adjusting bracket, and a first emission microscope. The first light-guiding cable is connected with a light generator. The light detector is connected with the second light-guiding cable. When the light generator generates a light beam, the light beam is emitted to a semiconductor light-guiding chip through the first light-guiding cable. The semiconductor light-guiding chip guides the light beam to the second light-guiding cable. The light detector receives the light beam through the second light-guiding cable to retrieve the energy of the light beam. The first emission microscope captures the leakage position of the semiconductor light-guiding chip where the light beam is emitted from the semiconductor light-guiding chip.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 6, 2025
    Inventors: CHI-LUN LIU, HSUEH-LIANG CHOU, TSUNG-YU LEE
  • Patent number: 12149601
    Abstract: A method for converting network packets and a circuit system are provided. The circuit system uses firmware therein to record tables for implementing packet conversion between two types of networks (IPv4 and IPv6). In the method, a process of mapping of address and port using encapsulation (MAP-E) or a process of mapping of address and port using translation (MAP-T) is determined according to IPv4 packets routing requirement to embody an uplink and a downlink packet conversion process. A content table stores an IPv6 packet header after the MAP-E or MAP-T process. A control table is referred to for controlling the fields to be updated when adding the IPv6 packet header. A forwarding mapping rule table is referred to for determining to convert a destination IP address of an uplink IPv6 packet, or both a source IP address and a destination IP address of a downlink IPv4 packet.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: November 19, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Tsung-Yin Su, Tsung-Yu Lee
  • Publication number: 20230107822
    Abstract: A method for converting network packets and a circuit system are provided. The circuit system uses firmware therein to record tables for implementing packet conversion between two types of networks (IPv4 and IPv6). In the method, a process of mapping of address and port using encapsulation (MAP-E) or a process of mapping of address and port using translation (MAP-T) is determined according to IPv4 packets routing requirement to embody an uplink and a downlink packet conversion process. A content table stores an IPv6 packet header after the MAP-E or MAP-T process. A control table is referred to for controlling the fields to be updated when adding the IPv6 packet header. A forwarding mapping rule table is referred to for determining to convert a destination IP address of an uplink IPv6 packet, or both a source IP address and a destination IP address of a downlink IPv4 packet.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 6, 2023
    Inventors: TSUNG-YIN SU, TSUNG-YU LEE
  • Publication number: 20170173567
    Abstract: A method of preparing selective catalytic reduction composite catalyst is provided. First, first metal compound support, second metal compound, third metal compound and water are mixed to formed a precursor solution. Then, dried mixture powder is formed from the precursor solution by a spray-drying process. Thereafter, a calcination process is performed on the dried mixture powder.
    Type: Application
    Filed: March 14, 2016
    Publication date: June 22, 2017
    Inventors: Hsun-Ling Bai, Liang-Yi Lin, Tsung-Yu Lee, You-Ren Zhang
  • Patent number: 7492179
    Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: February 17, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Chiu, Hsing-Ya Huo, Tsung-Yu Lee
  • Patent number: 7403864
    Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: July 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing Ya Huo, Chung-Lin Hsieh, Tsung-Yu Lee, Yang Yen-Ni
  • Publication number: 20080106278
    Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 8, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing Ya Huo, Chung-Lin Hsieh, Tsung-Yu Lee, Yang Yen-Ni
  • Publication number: 20070236238
    Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 11, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Chiu, Hsing-Ya Huo, Tsung-Yu Lee
  • Publication number: 20070048961
    Abstract: A semiconductor device and fabricating method thereof are provided. In the fabricating method, two trenches are formed in the substrate and, then the first dielectric layers is formed on the sidewalls of the trenches and a source/drain layer is formed in each trench. A second dielectric layer is formed on the substrate and the source/drain layer. Finally, a gate structure is formed on the second dielectric layer. The source/drain layers and the first dielectric layers are placed in trenches; therefore, device dimension can be reduced.
    Type: Application
    Filed: January 16, 2006
    Publication date: March 1, 2007
    Inventors: Ko-Hsing Chang, Wu-Tsung Chung, Tsung-Yu Lee