Patents by Inventor Tsung-Yu Wang
Tsung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145319Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
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Publication number: 20240128232Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Publication number: 20230367942Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 11790145Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: June 29, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 11487384Abstract: The invention provides a touch device and a communication method thereof. The touch device includes a display panel and a controller. The controller controls the display panel to perform a display driving operation and a touch sensing operation. The controller may transmit a first wireless signal to another slave communication device via the display panel in a touch sensing period. The controller may receive a second wireless signal sent by another master communication device via the display panel in the touch sensing period. When the touch device serves as one of a master communication device and a slave communication device, a time length of the touch sensing period is a first time length. When the touch device serves as the other of the master communication device and the slave communication device, the time length of the touch sensing period is a second time length greater than the first time length.Type: GrantFiled: September 16, 2021Date of Patent: November 1, 2022Assignee: Novatek Microelectronics Corp.Inventors: Tsung-Yu Wang, Yun-Hsiang Yeh, Yen-Heng Chen
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Publication number: 20220335192Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 11392742Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 5, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20210019464Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 10796055Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 22, 2019Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 10651208Abstract: A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.Type: GrantFiled: January 2, 2019Date of Patent: May 12, 2020Assignee: INNOLUX CORPORATIONInventors: Pei-Chieh Chen, Hung-Kun Chen, Tsung-Yu Wang, Ying-Tong Lin
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Publication number: 20200050725Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 10509881Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: September 28, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 10394404Abstract: A touch display panel includes a substrate, a first sensing electrode layer. The first sensing electrode layer is disposed on the substrate. The first sensing electrode includes a plurality of first metal conductive lines and a plurality of second metal conductive lines connected with the plurality of first metal conductive lines. The first and second metal conductive lines are respectively arranged along different directions. The outermost one of the plurality of first metal conductive line has a first protruding portion.Type: GrantFiled: April 23, 2018Date of Patent: August 27, 2019Assignee: INNOLUX CORPORATIONInventors: Tsung-Yu Wang, Pei-Chieh Chen, Chao-Hsiang Wang
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Patent number: 10324369Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.Type: GrantFiled: August 25, 2017Date of Patent: June 18, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
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Publication number: 20190139990Abstract: A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.Type: ApplicationFiled: January 2, 2019Publication date: May 9, 2019Inventors: Pei-Chieh CHEN, Hung-Kun CHEN, Tsung-Yu WANG, Ying-Tong LIN
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Publication number: 20190095569Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: CHIA-PING CHIANG, MING-HUI CHIH, CHIH-WEI HSU, PING-CHIEH WU, YA-TING CHANG, TSUNG-YU WANG, WEN-LI CHENG, HUI EN YIN, WEN-CHUN HUANG, RU-GUN LIU, TSAI-SHENG GAU
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Publication number: 20190064652Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
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Patent number: 10199398Abstract: A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.Type: GrantFiled: September 1, 2016Date of Patent: February 5, 2019Assignee: INNOLUX CORPORATIONInventors: Pei-Chieh Chen, Hung-Kun Chen, Tsung-Yu Wang, Ying-Tong Lin
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Publication number: 20180239467Abstract: A touch display panel includes a substrate, a first sensing electrode layer. The first sensing electrode layer is disposed on the substrate. The first sensing electrode includes a plurality of first metal conductive lines and a plurality of second metal conductive lines connected with the plurality of first metal conductive lines. The first and second metal conductive lines are respectively arranged along different directions. The outermost one of the plurality of first metal conductive line has a first protruding portion.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Inventors: Tsung-Yu WANG, Pei-Chieh CHEN, Chao-Hsiang WANG
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Patent number: 9977554Abstract: A touch display panel includes a substrate, a first electrode layer, and a second electrode layer. The first and second electrode layers are disposed on the substrate. The second electrode layer electrically connects to the first electrode layer and includes a plurality of sensing electrodes. Each sensing electrode includes a plurality of first conductive lines and a plurality of second conductive lines connected to each other. The first and second conductive lines are respectively arranged along first and second directions, wherein the second direction is different from the first direction. In one of two adjacent sensing electrodes, the outermost first conductive line has at least one first edge and at least one second edge connected to the first edge. The first edge corresponds to one of the second conductive lines of the other one of the two adjacent sensing electrodes, and has a curved shape.Type: GrantFiled: June 16, 2016Date of Patent: May 22, 2018Assignee: INNOLUX CORPORATIONInventors: Tsung-Yu Wang, Pei-Chieh Chen, Chao-Hsiang Wang