Patents by Inventor Tsung-Yuan C. Tai

Tsung-Yuan C. Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11301275
    Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Ashok Sunder Rajan, Richard A. Uhlig, Rajendra S. Yavatkar, Tsung-Yuan C. Tai, Christian Maciocco, Jeffrey R. Jackson, Daniel J. Dahle
  • Publication number: 20210405730
    Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Inventors: Brian J. Skerry, Ira Weiny, Patrick Connor, Tsung-Yuan C. Tai, Alexander W. Min
  • Patent number: 11201940
    Abstract: Technologies for flow rule aware exact match cache compression include multiple computing devices in communication over a network. A computing device reads a network packet from a network port and extracts one or more key fields from the packet to generate a lookup key. The key fields are identified by a key field specification of an exact match flow cache. The computing device may dynamically configure the key field specification based on an active flow rule set. The computing device may compress the key field specification to match a union of non-wildcard fields of the active flow rule set. The computing device may expand the key field specification in response to insertion of a new flow rule. The computing device looks up the lookup key in the exact match flow cache and, if a match is found, applies the corresponding action. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Yipeng Wang, Ren Wang, Antonio Fischetti, Sameh Gobriel, Tsung-Yuan C. Tai
  • Publication number: 20210367887
    Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: Ren Wang, Tsung-Yuan C. Tai, Yipeng Wang, Sameh Gobriel
  • Publication number: 20210273868
    Abstract: Technologies for monitoring network traffic include a computing device that monitors network traffic at a graphics processing unit (GPU) of the computing device. The computing device manages computing resources of the computing device based on results of the monitored network traffic. The computing resources may include one or more virtual machines to process network traffic that is to be monitored at the GPU the computing device. Other embodiments are described and claimed.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 2, 2021
    Inventors: Alexander W. Min, Jr-Shian Tsai, Janet Tseng, Kapil Sood, Tsung-Yuan C. Tai
  • Patent number: 11088951
    Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Ren Wang, Tsung-Yuan C. Tai, Yipeng Wang, Sameh Gobriel
  • Patent number: 11054884
    Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Brian J. Skerry, Ira Weiny, Patrick Connor, Tsung-Yuan C. Tai, Alexander W. Min
  • Patent number: 11042403
    Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilkerson, Karl I. Taht, Ren Wang, James J. Greensky, Tsung-Yuan C. Tai
  • Publication number: 20210180965
    Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.
    Type: Application
    Filed: July 28, 2020
    Publication date: June 17, 2021
    Inventors: Ren Wang, Zhonghong Ou, Arvind Kumar, Kristoffer Fleming, Tsung-Yuan C. Tai, Timothy J. Gresham, John C. Weast, Corey Kukis
  • Publication number: 20210141676
    Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.
    Type: Application
    Filed: January 19, 2021
    Publication date: May 13, 2021
    Inventors: Ren Wang, Daniel P. Daly, Antoine Kaufmann, Saikrishna Edupuganti, Tsung-Yuan C. Tai
  • Patent number: 11005884
    Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Sameh Gobriel, Christian Maciocco, Byron Marohn, Ren Wang, Tsung-Yuan C. Tai
  • Patent number: 10972371
    Abstract: Technologies for monitoring network traffic include a computing device that monitors network traffic at a graphics processing unit (GPU) of the computing device. The computing device manages computing resources of the computing device based on results of the monitored network traffic. The computing resources may include one or more virtual machines to process network traffic that is to be monitored at the GPU the computing device. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Alexander W. Min, Jr-Shian Tsai, Janet Tseng, Kapil Sood, Tsung-Yuan C. Tai
  • Publication number: 20210099398
    Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 1, 2021
    Inventors: Ren WANG, Tsung-Yuan C. TAI, Jr-Shian TSAI
  • Publication number: 20210089216
    Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 25, 2021
    Inventors: Yipeng WANG, Ren WANG, Sameh GOBRIEL, Tsung-Yuan C. TAI
  • Patent number: 10936490
    Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Edwin Verplanke, Stephen R. Van Doren, Ravishankar Iyer, Eric R. Wehage, Rupin H. Vakharwala, Rajesh M. Sankaran, Jeffrey D. Chamberlain, Julius Mandelblat, Yen-Cheng Liu, Stephen T. Palermo, Tsung-Yuan C. Tai
  • Patent number: 10929323
    Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
  • Patent number: 10904161
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for routing data packets in a quality of service (QoS) enabled content-based network or interconnect fabric. Various embodiments describe how to manage data flow based on content-based attribute vectors (AVs) indicating QoS requirements with respect to the data packets in networking or platform interconnects. A dynamic scheduling based on AV information may improve trafficking efficiency and optimize system performance.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Ren Wang, Ahmad A. Samih, Christian Maciocco, Andrew Brown, Tsung-Yuan C. Tai
  • Publication number: 20210004328
    Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Ren Wang, Andrew J. Herdrich, Yen-cheng Liu, Herbert H. Hum, Jong Soo Park, Christopher J. Hughes, Namakkal N. Venkatesan, Adrian C. Moga, Aamer Jaleel, Zeshan A. Chishti, Mesut A. Ergin, Jr-shian Tsai, Alexander W. Min, Tsung-yuan C. Tai, Christian Maciocco, Rajesh Sankaran
  • Publication number: 20200371914
    Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 26, 2020
    Inventors: Ren WANG, Yifan YUAN, Yipeng WANG, Tsung-Yuan C. TAI, Tony HURSON
  • Patent number: 10817425
    Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Ren Wang, Andrew J. Herdrich, Yen-cheng Liu, Herbert H. Hum, Jong Soo Park, Christopher J. Hughes, Namakkal N. Venkatesan, Adrian C. Moga, Aamer Jaleel, Zeshan A. Chishti, Mesut A. Ergin, Jr-shian Tsai, Alexander W. Min, Tsung-yuan C. Tai, Christian Maciocco, Rajesh Sankaran