Patents by Inventor Tsung-Yuan Lee
Tsung-Yuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971624Abstract: A display device includes a first display unit emitting a green light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak and an intensity of the first peak.Type: GrantFiled: July 6, 2023Date of Patent: April 30, 2024Assignee: InnoLux CorporationInventors: Hsiao-Lang Lin, Jia-Yuan Chen, Jui-Jen Yueh, Kuan-Feng Lee, Tsung-Han Tsai
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Publication number: 20240136484Abstract: An electronic device includes a substrate, a semiconductor unit and an insulating layer. The semiconductor unit is disposed on the substrate. The insulating layer is disposed on the semiconductor unit, and the insulating layer includes a first portion and a second portion connected to the first portion. In a top view, the first portion partially overlaps the semiconductor unit, the second portion does not overlap the semiconductor unit, and a part of an edge of the insulating layer is irregular.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: InnoLux CorporationInventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
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Publication number: 20240136344Abstract: A display device includes a substrate, at least one light emitting unit bound on the substrate, a transparency controllable unit disposed on the substrate, and an integrated circuit unit overlapped with the substrate. The integrated circuit unit includes a semiconducting structure and a conductive structure overlapped with the semiconducting structure. The integrated circuit unit is electrically connected to the at least one light emitting unit and the transparency controllable unit.Type: ApplicationFiled: September 17, 2023Publication date: April 25, 2024Applicant: InnoLux CorporationInventors: Jia-Yuan CHEN, Yu-Chia HUANG, Tsung-Han TSAI, Kuan-Feng LEE
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Publication number: 20240120451Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE, Yuan-Lin WU
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Patent number: 11939664Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Chun Hsieh, Tsung-Yu Tsai, Hsing-Yuan Huang, Chih-Chang Wu, Szu-Hua Wu, Chin-Szu Lee
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Publication number: 20240097034Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Publication number: 20240072018Abstract: Abstract of Disclosure A display device includes a blue sub-pixel including a plurality of first light emitting units in a number of N1, a green sub-pixel including a plurality of second light emitting units in a number of N2, and a red sub-pixel including a plurality of third light emitting units in a number of N3. The first light emitting units, the second light emitting units and the third light emitting units all emit lights of blue color, and a green wavelength conversion layer and a red wavelength conversion layer are so arranged that the blue light from the second light emitting units and the blue light from the third light emitting units go through the green wavelength conversion layer and the red wavelength conversion layer respectively. N1 is greater than or equal to 6. N1<N2 and N1<N3, wherein N2/N1 is between 2.1 and 3.68, and N3/N1 is between 1.52 and 2.53.Type: ApplicationFiled: November 5, 2023Publication date: February 29, 2024Applicant: InnoLux CorporationInventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee
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Patent number: 7205614Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.Type: GrantFiled: January 6, 2004Date of Patent: April 17, 2007Assignee: Faraday Technology Corp.Inventors: Sheng-Tai Young, Te-Sun Wu, Tsung-Yuan Lee, Chih-Kang Chiu
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Publication number: 20050145948Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.Type: ApplicationFiled: January 6, 2004Publication date: July 7, 2005Inventors: Sheng-Tai Young, Te-Sun Wu, Tsung-Yuan Lee, Chih-Kang Chiu