Patents by Inventor Tsung-Yueh Tsai
Tsung-Yueh Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100007010Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG
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Publication number: 20100007004Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
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Publication number: 20100007009Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG, Cheng Tsung HSU, Chih Cheng HUNG
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Publication number: 20100007011Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.Type: ApplicationFiled: July 13, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Ying HUNG, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong
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Publication number: 20090230526Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.Type: ApplicationFiled: August 15, 2008Publication date: September 17, 2009Inventors: Chien-Wen Chen, An-shih Tseng, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai
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Publication number: 20090230564Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.Type: ApplicationFiled: August 8, 2008Publication date: September 17, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung Yueh TSAI, Yi Shao Lai, Cheng Wei Huang
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Publication number: 20090175312Abstract: A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.Type: ApplicationFiled: January 8, 2009Publication date: July 9, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang
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Publication number: 20090096077Abstract: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.Type: ApplicationFiled: July 9, 2008Publication date: April 16, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang, Tsan-Hsien Chen
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Publication number: 20090051031Abstract: A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure.Type: ApplicationFiled: July 31, 2008Publication date: February 26, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai
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Publication number: 20090051048Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.Type: ApplicationFiled: August 13, 2008Publication date: February 26, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang
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Publication number: 20070284756Abstract: A stacked chip package is provided. The metal bumps disposed on the lower chip are encapsulated by a layer of non-conductive adhesive and the area around by the layer of non-conductive adhesive material is filled with another adhesive. Under such a configuration, it can prevent the upper chip from contacting the bonding wires connected to the lower chip and eliminate the fracture of the upper chip during the wire bonding process.Type: ApplicationFiled: January 17, 2007Publication date: December 13, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung Yueh TSAI, Yi Shao LAI
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Publication number: 20070222047Abstract: A semiconductor package structure includes a substrate, a first chip, a second chip, a wire, and an encapsulant. The substrate with a cavity has a first surface and a second surface. The cavity penetrates the first surface and the second surface. The first surface and the second surface have a first solder pad and a second solder pad respectively. The first chip having a first active surface and a first non-active surface is disposed inside the cavity. The first active surface has a first contact pad. The second chip having a second active surface and a second non-active surface is disposed on the second surface. The second non-active surface is adhered to the first non-active surface. The second active surface has a second contact pad. The wire is used for electrically connecting the second contact pad and the second solder pad. The encapsulant disposed on the substrate fills the cavity.Type: ApplicationFiled: November 21, 2006Publication date: September 27, 2007Inventors: Tsung-Yueh Tsai, Chang-Lin Yeh
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Patent number: 7071553Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.Type: GrantFiled: September 3, 2004Date of Patent: July 4, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Yueh Tsai, Sheng-Yang Peng
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Patent number: 7037750Abstract: A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.Type: GrantFiled: February 11, 2004Date of Patent: May 2, 2006Assignee: Advanced Semiconductor Engineering Inc.Inventors: Yu-Fang Tsai, Chin-Hsien Lin, Tsung-Yueh Tsai
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Patent number: 7026709Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.Type: GrantFiled: September 25, 2004Date of Patent: April 11, 2006Assignee: Advanced Semiconductor Engineering Inc.Inventors: Yu-Fang Tsai, Jung-Kun Kang, Tsung-Yueh Tsai
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Patent number: 7015065Abstract: A manufacturing method of a ball grid array package mainly comprises providing a carrier unit with an upper surface and a lower surface, mounting a plurality of solder balls on the lower surface of the carrier unit, disposing a protective layer below the lower surface to cover the solder balls, placing a chip on the upper surface of the carrier unit and electrically connecting the carrier and the chip, encapsulating the chip and removing the protective layer so as to form said ball grid array package.Type: GrantFiled: June 28, 2004Date of Patent: March 21, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Fang Tsai, Jung-Kun Kang, Tsung Yueh Tsai
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Patent number: 6873778Abstract: A fiber container receiving optical fibers has a body, a space defined in the body, a reel disposed inside the body, wherein a groove is defined around the periphery of the reel. The optical fibers are twisted around the reel and received in the groove. Furthermore, the fiber container is able to apply to the active/passive optical communication device, such as an erbium doped fiber amplifier (EDFA) or a dense wavelength division multiplexer (DWDM).Type: GrantFiled: November 12, 2002Date of Patent: March 29, 2005Assignee: Asia Optical Co., Inc.Inventors: Tsung-Yueh Tsai, Chin-Hsiang Wang, Yu-Ting Lee, Chih-Hsien Lin
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Patent number: 6854900Abstract: A method of fabricating a WDM unit consists of attaching a first and a second GRIN lenses to opposite faces of a WDM filter. A dual fiber pigtail and a single fiber pigtail are mounted in corresponding glass tubes. The glass tube with the dual fiber pigtail and the glass tube with the single fiber pigtail are mounted on the second GRIN lens and the first GRIN lens respectively. The position of the dual fiber pigtail and the single fiber pigtail are adjusted with respect to the second GRIN lens and the first GRIN lens respectively to obtain the best optical property. The invention prevents the WDM filter from tilting during temperature variation by sandwiching the WDM filter in between the two GRIN lenses, and further prevents the WDM unit from increasing the reflection loss and insertion loss.Type: GrantFiled: July 16, 2002Date of Patent: February 15, 2005Assignee: Asia Optical Co., Inc.Inventors: I-Jen Lai, Pie-Yau Chien, Chin-Hsiang Wang, Yu-Ting Lee, Tsung-Yueh Tsai, Chih-Hsien Lin
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Publication number: 20050023657Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.Type: ApplicationFiled: September 25, 2004Publication date: February 3, 2005Inventors: Yu-Fang Tsai, Jung-Kun Kang, Tsung-Yueh Tsai
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Publication number: 20050006756Abstract: The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.Type: ApplicationFiled: September 3, 2004Publication date: January 13, 2005Inventors: Tsung-Yueh Tsai, Sheng-Yang Peng