Patents by Inventor Tsung-Yung (Jonathan) Chang
Tsung-Yung (Jonathan) Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299420Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: June 12, 2015Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Publication number: 20150279450Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: ApplicationFiled: June 12, 2015Publication date: October 1, 2015Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Patent number: 9076553Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.Type: GrantFiled: November 13, 2013Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-jer Hsieh, Chiting Cheng, Chien-Kuo Su, Cheng Hung Lee, Tsung-Yung Jonathan Chang
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Patent number: 9058899Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: November 18, 2013Date of Patent: June 16, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-Yung Jonathan Chang
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Publication number: 20150131365Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-jer Hsieh, Chiting Cheng, Chien-Kuo Su, Cheng Hung Lee, Tsung-Yung Jonathan Chang
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Patent number: 8724420Abstract: An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.Type: GrantFiled: May 11, 2011Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiting Cheng, Chung-Cheng Chou, Tsung-yung Jonathan Chang
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Patent number: 8587992Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: GrantFiled: June 24, 2011Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Publication number: 20120327705Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Yi-Tzu Chen, Hau-Tai Shieh, Tsung-yung Jonathan Chang
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Publication number: 20120287736Abstract: An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiting Cheng, Chung-Cheng Chou, Tsung-yung Jonathan Chang
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Patent number: 8091000Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.Type: GrantFiled: August 13, 2009Date of Patent: January 3, 2012Assignee: Intel CorporationInventors: Tsung-Yung (Jonathan) Chang, Durgesh Srivastava, Jonathan Shoemaker, John Benoit
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Publication number: 20100058109Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.Type: ApplicationFiled: November 9, 2009Publication date: March 4, 2010Inventors: Tsung-Yung (Jonathan) Chang, Durgesh Srivastava, Jonathan Shoemaker, John Benoit
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Publication number: 20090300413Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.Type: ApplicationFiled: August 13, 2009Publication date: December 3, 2009Inventors: Tsung-Yung (Jonathan) Chang, Durgesh Srivastava, Jonathan Shoemaker, John Benoit
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Publication number: 20080010566Abstract: Systems and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Various techniques are provided for detecting a defect in a portion of memory and dynamically avoiding future attempts to access the defective portion of memory. More specifically, the techniques detect and avoid both hard and erratic errors.Type: ApplicationFiled: June 21, 2006Publication date: January 10, 2008Inventors: Tsung-Yung (Jonathan) Chang, Durgesh Srivastava, Jonathan Shoemaker, John Benoit