Abstract: A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.

Abstract: A sound effect power supply configuration includes a USB power supply source, an external audio source, a sound effect unit and an external speaker, wherein the USB power input terminal provides sound effect unit USB power source, for the sound effect unit after obtaining USB power source may receive the audio signals output by the external audio source, and after appropriately processing the audio, may drive the external speaker to generate sounds having high quality sound effect.

Abstract: A semiconductor structure for high voltage/high current MOS circuits is provided, including a deep N-well (NMD), a P-well (PW) disposed within NWD, a plurality of field oxide regions (FOX), a plurality of doping regions, including both N+ regions and P+ regions, disposed within NWD and PW, a gate (G) connected to a doping region, a bulk pad (B) connected to a doping regions, a source pad (S) connected to a doping regions and a drain pad (D) connected to a doping region. The top view of the present invention shows that the regions are of non-specific shapes and overlaid in a radial manner, with doping region connected to B being encompassed by doping region connected to S, which in turn encompassed by G, encompassed by FOX, encompassed by doping region connected to D.

Abstract: A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, the semiconductor circuit includes a plurality of semiconductor cells. Each semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Because conventional power strips are avoided, the present invention can reduce height of each semiconductor cell, and therefore increase integration of the semiconductor circuit (i.e., the integrated circuit).

Abstract: A lateral diffused metal-oxide-semiconductor field-effect transistor structure including a P substrate, an N+ buried layer, an N epitaxial layer, a P well, an N well, a drain region, a source region, and a body region is disclosed. The N+ buried layer is located between the P substrate and the N epitaxial layer, the P well contacts the N+ buried layer, the source region and the body region are located in the P well, the N well is located in the N epitaxial layer, and the drain region is located in the N well. When a high voltage is applied to the drain and the P substrate is grounded, a breakdown voltage with the P substrate is raised because of the N+ buried layer isolating the P substrate from the N epitaxial layer, so as to be able to avoid PN junction breakdown.

Abstract: A high coupling factor transformer and a manufacturing method thereof are provided. The transformer includes a primary winding and a secondary winding. The secondary winding is adjacent to the primary winding. The secondary winding and the primary winding induct with each other. The primary winding includes a plurality of first protruding portions, and the secondary winding includes a plurality of second protruding portions. The first protruding portions stretch to the secondary winding without electro-contact, and the second protruding portions stretch to the primary winding without electro-contact.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: A capacitor structure has a first electrode and a second electrode, which does not electrically connect to the first electrode. The first electrode has a plurality of first meshed conductive structures. The first meshed conductive structures have the same layout pattern, and are electrically connected to each other. The second electrode has a plurality of second meshed conductive structures. The second meshed conductive structures have the same layout pattern, and are electrically connected to each other. The first meshed conductive structures and the second meshed conductive structures are alternately stacked.

Abstract: A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: A frequency generator apparatus and a control circuit thereof are provided. The frequency generator apparatus comprises the control circuit and a frequency generator, wherein the control circuit contains an electric fuse (efuse). The control circuit outputs an enabling signal according to the state of the efuse. The frequency generator is coupled to the control circuit, receives the enabling signal, and decides to output a frequency signal or not according to the enabling signal.

Abstract: A high coupling factor transformer and a manufacturing method thereof are provided. The transformer includes a primary winding and a secondary winding. The secondary winding is adjacent to the primary winding. The secondary winding and the primary winding induct with each other. The primary winding includes a plurality of first protruding portions, and the secondary winding includes a plurality of second protruding portions. The first protruding portions stretch to the secondary winding without electro-contact, and the second protruding portions stretch to the primary winding without electro-contact.

Abstract: A frequency generator apparatus and a control circuit thereof are provided. The frequency generator apparatus comprises the control circuit and a frequency generator, wherein the control circuit contains an electric fuse (efuse). The control circuit outputs an enabling signal according to the state of the efuse. The frequency generator is coupled to the control circuit, receives the enabling signal, and decides to output a frequency signal or not according to the enabling signal.

Abstract: A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated circuit, a routing procedure is used to connect power of all cells arranged in the integrated circuit. Because power strips are avoided in each cell, the claimed invention can reduce layout height of each cell, and therefore increase integration of integrated circuits.

Abstract: A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, the semiconductor circuit includes a plurality of semiconductor cells. Each semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Because conventional power strips are avoided, the present invention can reduce height of each semiconductor cell, and therefore increase integration of the semiconductor circuit (i.e., the integrated circuit).

Abstract: A layout structure of semiconductor cells is described. The layout structure includes multiple semiconductor cells, wherein at least one pair of cells has an overlap member part between them, so that the area of the pair of cells is smaller than the sum of respective areas of the two cells.

Abstract: A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated circuit, a routing procedure is used to connect power of all cells arranged in the integrated circuit. Because power strips are avoided in each cell, the claimed invention can reduce layout height of each cell, and therefore increase integration of integrated circuits.

Abstract: A cell arrangement scheme is disclosed. A first cell comprising a PMOS and a NMOS, wherein the source of the PMOS is connected with a power line VDD by a first metal line, the source of the NMOS is connected to a power line GND by a second, the drains of the PMOS and NMOS connected together by a third metal line, and the gate of the PMOS and the NMOS are connected together by a poly line. A second cell comprising a PMOS and a NMOS, wherein the source of the PMOS is connected with a power line VDD by a first metal line, the source of the NMOS is connected to a power line GND by a second metal line, the drains of the PMOS and NMOS connected together by a third metal line, and the gate of the PMOS and the NMOS are connected together by a poly line. Partially overlapping the first cell in a such a way that the first and the second metal line of the first cell is overlapped and in contact with the first and the second metal line of the second cell respectively.

Abstract: A unified zero-reset phase is used in a dual-slope analog-to-digital converter (ADC) to: (1) derive a correction voltage to cancel any error due to offset and/or residue voltages in the components of the ADC in the subsequent integration phase and the de-integration phase; (2) reset the output of the integrator in the ADC to zero quickly when there is a overflow condition due to excessive analog input signals. The combined function is accomplished by negative feedback from the output of the comparator to the input of the buffer. The negative feedback resets the integrator output to zero quickly under overflow condition. The correction voltage is stored in the integrating capacitor and a coupling capacitor to the integrating amplifier.

Abstract: A charge pumping circuit generates a negative voltage equal in magnitude to the positive supply voltage. A non-overlapping clock is used to set the voltage across a first capacitor equal to the positive supply voltage through a MOS switch. This stored voltage is then transferred to a second capacitor through a second MOS switch to generate a negative voltage at one terminal of the second MOS switch. The use of MOS switches eliminates the threshold voltage drop if MOS diodes were used to charge the first capacitor or to transfer the voltage from the first capacitor to the second capacitor.